Table Of Contents - Altera DE5-NET User Manual

CHAPTER 1 OVERVIEW
1.1 G D
ENERAL ESCRIPTION
1.2 K F .......................................................................................................................................................... 5
EY EATURES
1.3 B D ...................................................................................................................................................... 6
LOCK IAGRAM
CHAPTER 2 BOARD COMPONENTS
2.1 B O .................................................................................................................................................. 10
OARD VERVIEW
2.2 C , S
ONFIGURATION TATUS AND
2.3 G U I
ENERAL SER NPUT
2.4 T S
EMPERATURE ENSOR AND
2.5 C C ...................................................................................................................................................... 19
LOCK IRCUIT
2.6 RS-422 S P .............................................................................................................................................. 21
ERIAL ORT
2.7 FLASH M ................................................................................................................................................... 22
EMORY
2.8 DDR3 SO-DIMM ................................................................................................................................................... 25
2.9 QDRII+ SRAM ...................................................................................................................................................... 32
2.10 SPF+ P .......................................................................................................................................................... 40
ORTS
2.11 PCI E ......................................................................................................................................................... 42
XPRESS
2.12 SATA .................................................................................................................................................................... 44
SYSTEM BUILDER
CHAPTER 3
3.1 I ....................................................................................................................................................... 48
NTRODUCTION
3.2 G D F
ENERAL ESIGN LOW
3.3 U S B
SING YSTEM UILDER
CHAPTER 4 FLASH PROGRAMMING
4.1 CFI F M M
LASH EMORY
4.2 FPGA C O
ONFIGURE PERATION
4.3 F P
LASH ROGRAMMING WITH
4.4 R F S
ESTORE ACTORY ETTINGS
PROGRAMMABLE OSCILLATOR
CHAPTER 5
5.1 O .............................................................................................................................................................. 62
VERVIEW
5.2 S 570 E RTL ......................................................................................................................................... 66
I XAMPLE BY
DE5-Net User Manual
........................................................................................................................................ 4
............................................................................................................................................ 4
.................................................................................................................. 10
S ..................................................................................................................... 11
ETUP
/O .............................................................................................................................. 14
UTPUT
F C ............................................................................................................ 18
AN ONTROL
......................................................................................................................... 48
......................................................................................................................................... 49
........................................................................................................................................ 50
................................................................................................................. 57
...................................................................................................................................... 57
AP
............................................................................................................................... 58
U D .......................................................................................................... 58
SERS ESIGN
................................................................................................................................. 60
................................................................................................. 62
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CONTENTS
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June 20, 2018