Analog Devices ADRV9001 User Manual page 89

Preliminary Technical Data
REF_CLK
MCS
SAMPLED
MCS
An external clock module is required to synchronize multiple ADRV9001 devices. Each ADRV9001 will receive a DEV_CLK and an MCS
signal. The MCS signals should arrive at all ADRV9001 devices within one DEV_CLK cycle, for the reason that it needs to be sampled by
the DEV_CLK mentioned above. For this reason, we recommend the layout to have equal-length traces between the external clock
module and each of the ADRV9001 devices. User will need to carefully tune the external clock module so that the pulses will arrive at all
ADRV9001 devices within one clock cycle time.
Setup time means the MCS positive edge has to arrive at least 5ns before DEV_CLK positive edge.
Hold time means the MCS negative edge has to arrive at least 5ns after DEV_CLK positive edge.
Setup/hold time are still being characterized and this is a preliminary result.
MCS pulses
The Figure 83 shows the MCS signal required to be received by ADRV9001. There are a total of 6 pulses. First 4 pulses are for the analog
clock divider synchronization, and the last 2 are for the digital clock divider synchronization. Together they will synchronize all internal
components of ADRV9001.
MCS
MCS
FIRST MCS
ANALOG
DEVICE CLOCK
DIVIDER
SYNCHRONIZATION
Pulse width and delay
Table 33 shows the minimum pulse width of each MCS pulse, as well as the wait time required after each pulse. The user should use this
reference to design MCS pulse generation.
Table 33. Minimum Time Requirement for MCS Pulse Width and Wait Time
Pulse No. Pulse Width (No. of Reference Clock Cycles)
1 ≥2
2 ≥2
3 ≥2
4 ≥2
5 ≥2
6 ≥2
SETUP HOLD
MCS SAMPLING USING POSITIVE EDGE OF REF_CLK
Figure 82 Sample MCS signal at rising edge of DEV_CLK
SECOND MCS THIRD MCS
ANALOG ANALOG
PLL REFERENCE PLL STATE
CLOCK DIVIDER
SYNCHRONIZATION SYNCHRONIZATION
Figure 83 MCS pulses for analog and digital synchronization
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FOURTH MCS
ANALOG
CLKGEN DIVIDER
MACHINE
SYNCHRONIZATION
Wait Time After the Pulse Tn (µs)
>1
>1
>1
>100
>100
>1
FIRST MCS SECOND MCS
DIGITAL DIGITAL
DIGITAL CLOCK RX DATA
DIVIDER INTERFACE
SYNCHRONIZATION SYNCHRONIZATION
UG-1828