Analog Devices ADRV9001 User Manual page 302

UG-1828
Clocks
The Clocks tab (Figure 283) provides access to the settings that determine device clock configuration. This page allows the user to:
• Set the device clock.
• Set the device clock frequency.
• Set the divisor value applied to the frequency at DEV_CLK_OUT.
• Enable/disable the DEV_CLK_OUT signal.
• Select the clock PLL type to be either high performance or low power (Note that LP PLL supports only certain sampling rates,
see Clock Generation section above for limitations).
• Select the Processor Clock Divisor value from 1, 2, and 4. Lower clock rate saves power. Changing the Processor Clock Divisor
value will have effects on the whole system from changing the power up time to tracking calibration times.
Figure 283. Clocks Configuration Tab
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Preliminary Technical Data