Analog Devices ADRV9001 User Manual page 57

Preliminary Technical Data
RX_DCLK_OUT
RX_STROBE_OUT
RX_STROBE_OUT
RX_DATA_OUT
Figure 35 illustrates the transmit CSSI interface (Tx) for a 16-bit data symbols.
TX_DCLK_OUT
TX_DCLK_IN
TX_STROBE_IN
TX_STROBE_IN
TX_DATA_IN
Receive CSSI Interface with 2×, 4×, and 8× Data Clock Rates
ADRV9001 receive CSSI supports the 2 times, 4 times, or 8 times of the data clock rate for some applications.
Figure 36, Figure 37, and Figure 38 illustrate the receive CSSI interface (Rx1 and Rx2) for 16-bit I/Q data sample with 2×, 4×, and 8×
clock rates. The strobe pulse validates the start of the 32-bit I and Q samples, the remaining data bits are ignored.
RX_DCLK_OUT
RX_STROBE_OUT
OR
RX_STROBE_OUT
RX_DATA_OUT
Figure 36. Receive CSSI Timing with 2× Data Clock Rate for 16-Bit I/Q Data Sample (MSB First), 32 Cycles
RX_DCLK_OUT
RX_STROBE_OUT
OR
RX_STROBE_OUT
RX_DATA_OUT
Figure 37. Receive CSSI Timing with 4× Data Clock Rate for 16-Bit I/Q Data Sample (MSB First), 96 Cycles
OR
S0_D15 S0_D14
Figure 34. Receive CSSI Timing for 16-Bit Symbols (MSB First)
OR
S0_D15 S0_D14
Figure 35. Transmit CSSI Timing for 16-Bit Symbols (MSB First)
16 CYCLES (I SAMPLE) 16 CYCLES (Q SAMPLE)
I0_D15 I0_D14 I0_D0 Q0_D15 Q0_D14
16 CYCLES (I SAMPLE) 16 CYCLES (Q SAMPLE)
I0_D15 I0_D14 I0_D0 Q0_D15 Q0_D14
S0_D8 S0_D7 S0_D6
S0_D8 S0_D7 S0_D6
32 CYCLES (NO SAMPLE)
Q0_D0
96 CYCLES (NO SAMPLE)
Q0_D0
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UG-1828
S0_D0 S1_D15
S0_D0 S1_D15
I1_D15 I0_D14
I1_D15 I0_D14