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Tests
DS0 Tests
DS0 Self Test (End-to-End)
Note
The DS0-level test pattern generator and checker, used in Self Test and in the Circuit Delay test, tests for
bit alignment as well as for the integrity of data going through the network. The pattern is transmitted and
checked on bits 2 – 7 of the selected DS0. Bits 1 and 8 are not used. The remote DSU must conform to this
requirement.
DS0 Self Test turns on the DS0-level test pattern generator and checker in the DSU. The test can be
initiated from the terminal interface or by SNMP control. Use of this test requires coordination with
the remote site, either to establish a loopback or to activate a test pattern generator and checker
(using the same pattern) for an end-to-end test.
The illustration shows DS0 Self Test in use as an End-to-End Test. When coordinating this test with
the remote site, make sure that the same test pattern and the same DS0 are selected in both units.
TPG
DTE
Inter-
face
TPC
TPG = Test Pattern Generator
TPC = Test Pattern Checker
Figure 4-21
Circuit Delay
The DS0 Circuit Delay test computes, for a selected channel, round-trip transmission delay of an
internally-generated message from the local unit to the remote unit and back to the local. The de-
lay includes variables like circuit distance, transmission path, etc. Hence, no figures of acceptable
delay are presented here. The result is an indication of network response time and throughput that
can be compared to results of the same test repeated under similar conditions at other times.
The DS0 Circuit Delay test can be commanded by means of the terminal interface or by SNMP
control.
076R155-000
Issue 7
SC 553 DSU
TX
Driver
Framer
Network
Analog
Receiver
DS0 End-to-End Self Test
SpectraComm 553 Fractional T1 DSU
Installation and Operation Manual
Remote DSU
Analog
Receiver
Framer
TX
Driver
Test pattern is transmitted and
monitored only on the selected DS0
DS0 Tests
TPC
DTE
Inter-
face
TPG
4-19
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