Part 3: Ddr3 Dram - Alinx ZYNQ7000 FPGA User Manual

Part 3: DDR3 DRAM

The AX7450 FPGA development board is equipped with 6 Micron (Micron)
512MB DDR3
MT41K256M16HA-125). The PS mounts 2 slices to form a 32-bit data width,
and the PL end mounts 4 slices to form a 64-bit data width. The DDR3 SDRAM
on the PS side can run at a maximum speed of 533MHz (data rate 1066Mbps),
and two DDR3 storage systems are directly connected to the memory interface
of the BANK 502 of the ZYNQ processing system (PS). The maximum
operating speed of DDR3 SDRAM on the PL side can reach 800MHz (data rate
1600Mbps), and four DDR3 storage systems are connected to the BANK33
and BANK34 interfaces of the FPGA. The specific configuration of DDR3
SDRAM is shown in Table 3-1.
Bit Number
U5,U6,U8,U9,U11,U12
The hardware design of DDR3 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR3.
The hardware connection of the DDR3 DRAM on the PS side is shown in
Figure 3-1:
12 / 54
ZYNQ FPGA Development Board AX7450 User Manual
chips, model
Chip Model
MT41J256M16HA-125
Table 3-1: DDR3 SDRAM Configuration
Amazon Store: https://www.amazon.com/alinx
MT41J256M16HA-125
Capacity
256M x 16bit
(compatible with
Factory
Micron