Cypress PSoC 64 Secure Boot Manual page 39

Table 5-1. Pin Details of J1 and J2 Headers
PSoC 64 "Secure Boot" Prototyping Board
Pin
J2_01
J2_02
J2_03
J2_04
J2_05
J2_06
J2_07
J2_08
J2_09
J2_10
J2_11
J2_12
J2_13
J2_14
J2_15
J2_16
J2_17
J2_18
J2_19
J2_20
J2_21
* Note: P6_VDD and VBACKUP should never exceed 3.6 V.
CY8CPROTO-064B0S3 PSoC 64 "Secure Boot" Prototyping Kit Guide, Doc. # 002-29505 Rev. *B
GPIO Header (J2)
Signal Description
VDDUSB USB Power
GND Ground
VREF SAR ADC Vref
P8[1] GPIO
P8[0] GPIO
P10[5] GPIO
P10[4] GPIO
P10[3] GPIO
P10[2] GPIO
P10[1] GPIO
P10[0] GPIO
GND Ground
P6[3] GPIO
P0[3] GPIO
P0[2] GPIO
P7[3] GPIO
P7[2] GPIO
P7[1] GPIO
P7[0] GPIO
VIN Input Voltage
GND Ground
PSoC 64 "Secure Boot" Prototyping Board
GPIO Header (J1)
Pin Signal
J1_01 VBACKUP* Backup Power
J1_02 GND Ground
J1_03 VCC_FLASH QSPI Flash Power
J1_04 P0[4] GPIO/User SW2
]
J1_05 GPIO
P0[5
J1_06 P5[7] GPIO
J1_07 P5[6] GPIO
J1_08 P9[3] GPIO
J1_09 P9[2] GPIO
J1_10 P9[1] GPIO
J1_11 P9[0] GPIO
J1_12 GND Ground
J1_13 P2[6] GPIO
J1_14 P2[5] GPIO
J1_15 P2[4] GPIO
J1_16 P2[3] GPIO
J1_17 P2[2] GPIO
J1_18 P2[1] GPIO
J1_19 P2[0] GPIO
J1_20 P6_VDD* Target Voltage Input
J1_21 GND Ground
Hardware
Description
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