Cypress PSoC 4 Manuals

Cypress PSoC 4 Manuals

Manuals and User Guides for Cypress PSoC 4. We have 2 Cypress PSoC 4 manuals available for free PDF download: Architecture Technical Reference Manual, Manual

Cypress PSoC 4 Architecture Technical Reference Manual

Cypress PSoC 4 Architecture Technical Reference Manual (178 pages)

Brand: Cypress | Category: Microcontrollers | Size: 1 MB

Table of Contents

Table of Contents
5
Section A: Overview

11
- 1 Introduction
  
  13
  - Top Level Architecture
    13
  - CPU System
    14
    
    Processor
    14
    
    Interrupt Controller
    14
  - Features
    14
  - Fixed-Function Digital
    15
    
    Timer/Counter/Pwm Block
    15
    
    Serial Communication Blocksi2C Block
    15
  - Memory
    15
  - Special Function Peripherals
    15
    
    Capsense
    15
  - System-Wide Resources
    15
    
    Clocking System
    15
    
    Power System
    15
    
    Gpio
    15
  - Program and Debug
    16
- 2 Getting Started
  
  17
  - Support
    17
  - Product Upgrades
    17
  - Development Kits
    17
  - Application Notes
    17
- 3 Document Construction
  
  19
  - Major Sections
    19
  - Documentation Conventions
    19
    
    Register Conventions
    19
    
    Numeric Naming
    19
    
    Units of Measure
    20
    
    Acronyms
    20
Section B: CPU System

23
- 4 Cortex-M0 CPU
  
  25
  - Features
    25
  - Address Map
    26
  - Block Diagram
    26
  - How It Works
    26
  - Registers
    27
  - Instruction Set
    28
    
    Address Alignment
    29
    
    Memory Endianness
    29
  - Operating Modes
    28
  - Debug
    29
  - Systick Timer
    29
- 5 Interrupts
  
  31
  - Features
    31
  - How It Works
    31
  - Interrupts and Exceptions - Operation
    32
    
    Interrupt/Exception Handling
    32
    
    Level and Pulse Interrupts
    32
    
    Exception Vector Table
    33
  - Exception Sources
    33
    
    Reset Exception
    33
    
    Non-Maskable Interrupt (NMI) Exception
    34
    
    Hardfault Exception
    34
    
    Supervisor Call (Svcall) Exception
    34
    
    Pendsv Exception
    34
    
    Systick Exception
    35
  - Interrupt Sources
    35
  - Exception Priority
    35
  - Enabling and Disabling Interrupts
    36
  - Exception States
    36
    
    Pending Exceptions
    36
  - Stack Usage for Exceptions
    37
  - Interrupts and Low-Power Modes
    37
  - Exceptions - Initialization and Configuration
    38
  - Registers
    38
  - Associated Documents
    38
Section C: Memory System

39
- 6 Memory Map
  
  41
- Features
  41
- How It Works
  41
Section D: System Resources Subsystem (SRSS)

43
- 7 I/O System
  
  45
  - Features
    45
  - GPIO Interface Overview
    45
  - I/O Cell Architecture
    46
    
    Digital Input Buffer
    47
    
    Digital Output Driver
    48
  - Behavior in Low-Power Modes
    51
  - High-Speed I/O Matrix
    51
  - I/O State on Power up
    51
  - Interrupt
    51
  - Peripheral Connections
    53
    
    Firmware Controlled GPIO
    53
    
    Capsense
    53
    
    Timer, Counter, and Pulse Width Modulator (TCPWM) Block
    53
  - Registers
    53
- 8 Clocking System
  
  55
  - Block Diagram
    55
  - Clock Sources
    56
    
    Internal Main Oscillator
    56
    
    Internal Low-Speed Oscillator
    57
    
    External Clock (EXTCLK)
    57
  - Clock Distribution
    57
    
    HFCLK Input Selection
    57
    
    HFCLK Predivider Configuration
    58
    
    SYSCLK Prescaler Configuration
    58
    
    Peripheral Clock Divider Configuration
    58
  - Low-Power Mode Operation
    59
  - Register List
    59
- 9 Power Supply and Monitoring
  
  61
  - Block Diagram
    62
  - Power Supply Scenarios
    63
    
    Single 1.8 V to 5.5 V Unregulated Supply
    63
    
    Direct 1.71 V to 1.89 V Regulated Supply
    63
    
    VDDIO Supply
    64
  - How It Works
    64
    
    Regulator Summary
    64
  - Voltage Monitoring
    65
    
    Power-On-Reset (POR)
    65
  - Register List
    65
- 10 Chip Operational Modes
  
  67
  - Boot
    67
  - User
    67
  - Privileged
    67
  - Debug
    67
- 11 Power Modes
  
  69
  - Active Mode
    70
  - Sleep Mode
    70
  - Deep-Sleep Mode
    70
  - Power Mode Summary
    71
  - Low-Power Mode Entry and Exit
    72
  - Register List
    72
- 12 Watchdog Timer
  
  73
  - Features
    73
  - Block Diagram
    73
  - How It Works
    73
    
    Enabling and Disabling WDT
    74
    
    WDT Interrupts and Low-Power Modes
    75
    
    WDT Reset Mode
    75
  - Register List
    75
- 13 Reset System
  
  77
  - Reset Sources
    77
    
    Power-On Reset
    77
    
    Brownout Reset
    77
    
    Watchdog Reset
    77
    
    Software Initiated Reset
    78
    
    External Reset
    78
    
    Protection Fault Reset
    78
  - Identifying Reset Sources
    78
  - Register List
    78
- 14 Device Security
  
  79
  - How It Works
    79
    
    Flash Security
    80
Section E: Digital System

81
- 15 Inter-Integrated Circuit (I2C)
  
  83
  - Features
    83
  - General Description
    83
    
    Terms and Definitions
    84
    
    I2C Modes of Operation
    84
    
    Easy I2C (EZI2C) Protocol
    86
    
    I2C Registers
    87
    
    I2C Interrupts
    88
    
    Enabling and Initializing the I2C
    88
    
    Internal and External Clock Operation in I2C
    89
    
    Wake up from Sleep
    91
    
    Master Mode Transfer Examples
    92
    
    Slave Mode Transfer Examples
    94
    
    EZ Slave Mode Transfer Example
    96
    
    Multi-Master Mode Transfer Example
    98
- 16 Timer, Counter, and PWM
  
  101
  - Features
    101
  - Block Diagram
    101
    
    Enabling and Disabling Counter in TCPWM Block
    102
    
    Clocking
    102
    
    Events Based on Trigger Inputs
    103
    
    Output Signals
    104
    
    Power Modes
    105
  - Modes of Operation
    106
    
    Timer Mode
    107
    
    Capture Mode
    110
    
    Quadrature Decoder Mode
    112
    
    Pulse Width Modulation Mode
    115
    
    Pulse Width Modulation with Dead Time Mode
    119
    
    Pulse Width Modulation Pseudo-Random Mode
    121
  - TCPWM Registers
    123
Section F: Analog System

125
- 17 Capsense
  
  127
- Block Diagram
  127
- Features
  127
- How It Works
  128
- Capsense CSD Sensing
  129
  - GPIO Cell Capacitance to Current Converter
    129
  - Capsense Clock Generator
    131
  - Sigma Delta Converter
    131
- Capsense CSD Shielding
  133
  - CMOD Precharge
    134
- General-Purpose Resources: Idacs and Comparator
  135
- Register List
  135
Section G: Program and Debug

137
- 18 Program and Debug Interface
  
  139
  - Features
    139
  - Functional Description
    139
  - Serial Wire Debug (SWD) Interface
    140
    
    SWD Timing Details
    141
    
    ACK Details
    141
    
    Turnaround (Trn) Period Details
    141
  - Cortex-M0 Debug and Access Port (DAP)
    142
    
    Debug Port (DP) Registers
    142
    
    Access Port (AP) Registers
    142
  - Programming the Psoc 4 Device
    143
    
    SWD Port Acquisition
    143
    
    SWD Programming Mode Entry
    143
    
    SWD Programming Routines Executions
    143
  - Psoc 4 SWD Debug Interface
    144
    
    Debug Control and Configuration Registers
    144
    
    Breakpoint Unit (BPU)
    144
    
    Data Watchpoint (DWT)
    144
    
    Debugging the Psoc 4 Device
    144
  - Registers
    145
- 19 Nonvolatile Memory Programming
  
  147
  - Features
    147
  - Functional Description
    147
  - System Call Implementation
    148
  - Blocking and Non-Blocking System Calls
    148
    
    Performing a System Call
    148
  - System Calls
    149
    
    Silicon ID
    149
    
    Configure Clock
    150
    
    Load Flash Bytes
    151
    
    Write Row
    152
    
    Program Row
    152
    
    Erase All
    153
    
    Checksum
    153
    
    Write Protection
    154
    
    Non-Blocking Write Row
    155
    
    Non-Blocking Program Row
    156
    
    Resume Non-Blocking
    157
  - System Call Status
    158
  - Non-Blocking System Call Pseudo Code
    159
Glossary

161

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Cypress PSoC 4 Manual

Cypress PSoC 4 Manual (110 pages)

Brand: Cypress | Category: Microcontrollers | Size: 8 MB

Table of Contents

Table of Contents
3
Safety Information

5
1 Introduction

7
- Kit Contents
  7
- Psoc Creator
  9
- Getting Started
  9
- Additional Learning Resources
  9
- Technical Support
  9
- Document Revision History
  10
- Documentation Conventions
  10
2 Software Installation

11
- Install Kit Software
  11
- Install Hardware
  12
- Install Software
  12
- Uninstall Software
  13
- Develop Code Fast and Easy with Code Examples
  13
- Open an Example Project in Psoc Creator
  15
3 Kit Operation

17
4 Hardware

27
- Board Details
  27
- Theory of Operation
  29
- Functional Description
  30
  - Psoc 4
    30
  - Psoc 5LP
    31
  - Power Supply System
    33
  - Programming Interface
    35
  - Arduino Compatible Headers (J1, J2, J3, J4, and J12 - Unpopulated)
    36
  - Digilent Pmod Compatible Header (J5 - Unpopulated)
    38
  - Psoc 5LP GPIO Header (J8)
    39
  - Capsense Slider
    40
  - Pioneer Board Leds
    41
  - Push Buttons
    42
5 Code Examples

43
- Project: Blinking LED
  46
  - Project Description
    46
  - Hardware Connections
    46
  - Flow Chart
    47
  - Verify Output
    47
- Project: PWM
  49
  - Project Description
    49
  - Hardware Connections
    49
  - Flow Chart
    50
  - Verify Output
    51
- Project: Deep Sleep
  51
  - Project Description
    51
  - Hardware Connections
    51
  - Flow Chart
    52
  - Verify Output
    53
- Project: Capsense
  53
  - Capsense (Without Tuning)
    53
  - Capsense (with Tuning)
    55
6 Advanced Topics

63
Appendix

101
- CY8CKIT-042 Schematics
  101
- Pin Assignment Table
  104
- Program and Debug Headers
  106
- Use of Zero-Ohm Resistors and no Load
  107
- Error in Firmware/Status Indication in Status LED
  107
- Bill of Materials (BOM)
  108
- Regulatory Compliance Information
  110

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