Kit Operation; Theory Of Operation - Cypress PSoC 64 Secure Boot Manual

3.

Kit Operation

This chapter introduces you to various features of the CY8CPROTO-064B0S3 PSoC 64 "Secure
Boot" Prototyping Kit, including the theory of operation and the onboard KitProg3 programming and
debugging functionality, USB-UART and USB-I2C bridges.
3.1

Theory of Operation

The CY8CPROTO-064B0S3 PSoC 64 "Secure Boot" Prototyping Kit is built around the PSoC 64
chip. Figure 3-1
the device
Figure 3-1. PSoC 64 Block Diagram
Color Key:
Power Modes and Domains
System LP/ULP Mode
CPUs Active/Sleep
System
DeepSleep Mode
System
Hibernate Mode
Backup
Domain
CY8CPROTO-064B0S3 PSoC 64 "Secure Boot" Prototyping Kit Guide, Doc. # 002-29505 Rev. *B
shows the block diagram of the PSoC 64 device. For details of device features, see
datasheet.
PSoC 64 "Secure Boot" MCU
CYB06445LQI-S3D42
System Resources
Power Clocks
OVP LVD IMO ECO
POR BOD FLL 2x PLL
Buck Regulator 2x MCWDT
ILO WDT
XRES Reset
RTC WCO
Backup Regs PMIC Control
CPU Subsystem
Cortex M4F CPU
150/50 MHz, 1.1/0.9 V
SWJ, ETM, ITM, CTI
Cortex M0+ CPU
100/25 MHz, 1.1/0.9 V
SWJ, MTB, CTI
3x DMA
Controller
Crypto
DES/TDES, AES, SHA, CRC,
TRNG, RSA/ECC
Accelerator
Flash
512 KB + 32 KB + 32 KB
8 KB cache for each CPU
SRAM
256 KB
ROM
64 KB
Programmable Analog
SAR ADC 12 bit
Temperature Sensor
SCB
USB
PHY
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