Digi ConnectCore 8X Hardware Reference Manual page 16

The ConnectCore 8X System-on-module
Input rail
VDD_ENET0
VDD_ESAI_SPDIF
VDD_SPI_SAI
VDD_QSPI0B
VDD_CSI
USB_OTG1_VBUS
Note The CPU input power rails on the table above power different IO rings (pads) of the processor.
They can remain unconnected and the system will be still functional, as is the case in a castellated
design where some of these supplies are not available. However, the associated pads will remain
unpowered, and therefore not available.
See the External signals and pin multiplexing
associated to each pad of the module.
Three additional power domains of the CPU are connected to the module LGA pads, which are
associated in the SOM to the following power rails:
VDD_PCIE_DIG: internally tied to 3V3.
n
3V3_RF: internally tied to 3V3.
n
NVCC_MIPI_CSI_DSI: internally tied to 1V8.
n
Unless otherwise noted, 3V3_RF and NVCC_MIPI_CSI_DSI must not be connected to external circuitry.
In non-wireless variants,
VDD_PCIE_DIG must be powered externally in order to use the PCIe interface.
ConnectCore® 8X System-on-Module Hardware Reference Manual
Device
being Internal power domains being
powered powered
i.MX 8X CPU VDD_ENET0_VSELECT_1P8_2P5_3P3
n
VDD_ENET0_1P8_2P5_3P3
n
VDD_ENET_MDIO_1P8_3P3
n
i.MX 8X CPU
VDD_ESAI_SPDIF_1P8_2P5_3P3
i.MX 8X CPU
VDD_SPI_SAI_1P8_3P3
i.MX 8X CPU
VDD_QSPI0B_1P8_3P3
i.MX 8X CPU VDD_TMPR_CSI_1P8_3P3
n
VDD_CSI_1P8_3P3
n
i.MX 8X CPU
USB_OTG1_VBUS
for a complete description of the power group
Power interfaces
Description
Input power supply
for the ENET0
interface, including
the MDIO bus.
Because all ENET0-
related CPU blocks
are powered from
the same power rail,
2.5V configuration is
not available. (The
MDIO bus does not
work at this
voltage.)
Input power supply
for ESAI0 and
SPDIF0 interfaces.
Input power supply
for SAI0, SAI1, SPI0
and SPI2 interfaces.
Input power supply
for QSPI0B
interface.
Input power supply
for CSI interface.
Input power supply
for the USB1
interface VBUS.
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