Cgfsysena] (Supply And Stop Register A For Fsysh) - Toshiba TXZ+ Series Reference Manual

Bit Bit Symbol
7 IPMENB07
6 IPMENB06
5 IPMENB05
4 IPMENB04
3 IPMENB03
2 IPMENB02
1 IPMENB01
0 IPMENB00
Note1: Even if the initial value of the register is set to stop of the clock, the clock is supplied during the reset.
Note2: Write "0" for bit of function that does not exist in TMPM4KM, TMPM4KL and TMPM4KH. For details,
refer to "1.5. Information according to product".

1.4.2.9. [CGFSYSENA] (Supply and stop register A for fsysh)

Bit Bit Symbol
31:2 -
1 IPENA01
0 IPENA00
Note: Even if the initial value of the register is set to stop of the clock, the clock is supplied during the reset.
After reset Type
Clock enable of A-ENC32 ch1
0 R/W
0: Clock stop
1: Clock supply
Clock enable of A-ENC32 ch0
0 R/W
0: Clock stop
1: Clock supply
Clock enable of OPAMP Unit A/B/C
0 R/W
0: Clock stop
1: Clock supply
Clock enable of ADC Unit C (TSEL18)
0 R/W
0: Clock stop
1: Clock supply
Clock enable of ADC Unit B (TSEL17)
0 R/W
0: Clock stop
1: Clock supply
Clock enable of ADC Unit A (TSEL16)
0 R/W
0: Clock stop
1: Clock supply
Clock enable of T32A ch05 (TSEL40,41,42)
0 R/W
0: Clock stop
1: Clock supply
Clock enable of T32A ch04 (TSEL37,38,39)
0 R/W
0: Clock stop
1: Clock supply
After reset Type
0 R Read as "0"
Clock enable of RAMP ch0
0 R/W
0: Clock stop
1: Clock supply
Clock enable of CRC
0 R/W
0: Clock stop
1: Clock supply
38 / 64
TMPM4K Group(2)
Clock Control and Operation Mode
Function
Function
TXZ+ Family
2021-06-15
Rev. 1.1