The Directions For A Warming-Up Timer; Clock Multiplying Circuit (Pll) For Fsys; A Pll Setup After Reset Release - Toshiba TXZ+ Series Reference Manual

1.2.4.2. The directions for a warming-up timer

The directions for a warming-up function are explained.
(1) Selection of a clock
In a high speed oscillation, the clock classification (internal oscillation/external oscillation) counted with a
warming-up timer is selected by [CGWUPHCR]<WUCLK>.
(2) Calculation of warming-up timer setting value
The warming-up time can set any value to the timer for a high speed oscillation. Please compute and set up
from the formula.
(3) The start of warming-up, and a termination Confirmation
When software (command) performs the start of warming-up, starting warming-up count is carried out by
setting [CGWUPHCR]<WUON> to "1". Termination is confirmed with [CGWUPHCR]<WUEF> that
becomes from "1" to "0". "1" shows that it is warming-up and "0" shows termination. After a counting end,
a timer is reset and returns to an initial state.
It is not forced to terminate, although "0" is written to [CGWUPHCR]<WUON> during timer operation.
Writing "0" is disregarded.
Note: Since it is operating with the oscillating clock, a warming-up timer includes an error, when Oscillation
frequency has fluctuation. Therefore, It serves an approximate time.

1.2.5. Clock multiplying circuit (PLL) for fsys

The clock multiplying circuit outputs the f
the frequency (6 MHz to 12 MHz) of the output clock fosc of the high speed oscillator.
So, it is possible to make input frequency to an oscillator low and to make an internal clock high speed by this
circuit.

1.2.5.1. A PLL setup after reset release

The PLL is disabled after reset release.
In order to use the PLL, set [CGPLL0SEL]<PLL0SET[23:0]> to a multiplication value while [CGPLL0SEL]
<PLL0ON> is "0". Then wait until approximately 100 µs has elapsed as a PLL initial stabilization time, and set
<PLL0ON> to "1" to start PLL operation. After that, to use f
approximately 400 µs has elapsed as a lock up time. Then set [CGPLL0SEL]<PLL0SEL> to "1".
Note that a time is required until PLL operation becomes stable using the warming-up function, etc.
clock (maximum 160MHz) multiplied by the optimum condition for
PLL
clock which is multiplied fosc, wait until
PLL
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TMPM4K Group(2)
Clock Control and Operation Mode
TXZ+ Family
2021-06-15
Rev. 1.1