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POWR607 Device
This board features the POWR607, an in-system programmable, mixed-signal PLD that integrates high-perfor-
mance analog voltage monitors, 4 timer counter blocks, and a 16-macrocell programmable logic device. A com-
plete description of this device can be found in the DS1011,
Demonstration Designs
Lattice provides two demos that illustrate key applications of the Power Manager II devices POWR607 and
POWR6AT6:
• Processor Support - Demonstrates the POWR607 as a power manager for a processor, DSP, ASSP, or ASIC. It
integrates three functions traditionally covered by discrete ICs: voltage supervisor, reset generator, and watch-
dog timer. The programmable features of the POWR607 highlight its flexibility to be used in a variety of system
support roles. The processor support demo design is pre-loaded into the POWR607 by Lattice.
Note: The processor support demo program (JEDEC) differs slightly from the Initial Factory Configuration
described in DS1011,
active-low in the factory configuration.
• Voltage Monitoring - Shows application of the ispPAC-POWR6AT6 to provide supply measurements via an I
interface. The voltage monitoring support demo design is pre-programmed into the POWR6AT6 by Lattice with
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the I
C address of 0x6A.
Note: It is possible that you may obtain your POWR607 board after it has been reprogrammed. To restore the
factory default demo and program it with other Lattice-supplied examples see the
Download Windows Hardware Drivers
Processor Support Demo
The processor support demo is pre-programmed into the non-volatile elements of the POWR607 and POWR6AT6
devices and is operational upon power-up. The design provides the following features:
• Detect voltage supply violations and assert a CPU reset if a fault occurs.
• Provide a 500ms, 2 sec, 10 sec, or 1 min period watchdog timer and assert a watchdog timer interrupt if a timer
expires before a watchdog trigger interrupt occurs.
• Assert CPU reset pulses if manual reset of the board occurs. Provide an optional 200ms pulse stretch of the
reset.
• De-bounce manual reset input.
A PAC-Designer software project (.pac) defines the analog trip points for the POWR607 voltage monitors, timer-
counter period, and supervisory equations that define logical functions.
ispPAC-POWR607 Data
sections of this document.
POWR607/6AT6 Evaluation Board
ispPAC-POWR607 Data
Sheet. WDT_Intr output is active-high in the demo program, and
5
Sheet.
Download Demo Designs
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C
and
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