Lattice Semiconductor POWR607 User Manual page 12

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Figure 4. POWR607/6AT6 Evaluation Board Block Diagram
3.3V
2.5V Potentiometer
1.8V
Pushbutton
Switch SW2
Pushbutton
Switch SW3
A/Mini-B
USB Cable
USB Mini B
Socket
Controller
Table 2 describes the components on the board and the interfaces it supports.
Table 2. POWR607/6AT6 Evaluation Board Components and Interfaces
Component/Interface
Circuits
Pulse Stretch Circuit
USB Controller
USB Mini B Socket
Components
Power Manager II
Power Manager II
Interfaces
8x1 Header Landing
8x1 Header Landing
14x2 Header
5 LEDs
DIP Switch
Push-button Switches
Slide Potentiometer
VMON1
Slide
VMON2
VMON3
DIP Switch
SW1A
VMON [4:6] 4
IO_[3:5]
DIP Switch
SW1B,C,D
IN1
IN2
JTAG
Header
USB
I2C
2
VMON
VMON_GS 3
JTAG
Type
Schematic Reference
Circuit
Q4, D10, D11
Circuit
U8:FT2232H
I/O
J1:USB_MINI_B
Mixed Signal IC U3: ispPAC-POWR6AT6
Mixed Signal IC U1:ispPAC-POWR607
I/O
J2:I2C
I/O
J3:JTAG Interface
I/O
J4:HEADER 14X2
Output
D7-D0
I/O
SW1A, B, C, and D
I/O
SW2:Reset, SW3:WD_Trigger
I/O
R16
Power Manager II
3
POWR607
ispPAC-
POWR607-01SN24I
6
Power Manager II
POWR6AT6
ispPAC-
POWR6AT6-01SN32I
12
POWR607/6AT6 Evaluation Board
5
IO_[1:5]
5 LEDs
IO_2
Pulse Stretch
Circuit
VMON [1:6]
6
VMON_GS[4:6]
3
TRIM_[4:6]
3
IO_[1:5]
5
IN_[1:2]
2
VRAIL[4:6]
3
HVOUT[1:2]
2
TRIM_[4:6] 3
I2C
2
I2C
Header
Description
Stretch watchdog interrupt pulse outputs to
40ms.
USB-to-JTAG interface.
Programming and debug interface.
Voltage monitor, margin, trim.
Mixed Signal Device.
2
I
C interface.
JTAG interface.
User-definable I/O.
User-definable LEDs, I/O1 to I/O5.
4-bit DIP switch.
General-purpose push buttons.
Potentiometer tied to 3.3 V rail. Emulates
brown-out 2.5 V conditions at VMON2 inputs
of POWR607 and POWR6AT6.
LED D11
24
Header 14x2

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