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Pin
Key E*
Signal
25
Key
26
Key
27
Key
28
Key
29
Key
30
Key
31
Key
32
UART_TX
33
GND
34
UART_CTS
35
PET0+
36
UART_RTS
37
PET0-
38
Clink_RST
39
GND
40
Clink_DATA
41
PER0+
42
Clink_CLK
43
PER0-
44
-
45
GND
46
-
47
REFCLK0+
48
-
49
REFCLK0-
50
SUSCLK
51
GND
52
PERST0#
53
CLKREQ0#
54
W_DISABLE2#
55
PEWAKE0#
56
W_DISABLE1#
57
GND
58
-
59
-
60
-
61
-
62
-
63
GND
64
-
65
-
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Description
UART data output
Ground
UART clear to send
PCIe Lane 0 Tx pair (+)
UART request to send
PCIe Lane 0 Tx pair (-)
Wi-Fi CLINK host bus reset
Ground
Wi-Fi CLINK host bus data
PCIe Lane 0 Rx pair (+)
Wi-Fi CLINK host bus clock
PCIe Lane 0 Rx pair (-)
Ground
PCIe reference clock pair (+)
PCIe reference clock pair (-)
32.768 kHz clock supply input
Ground
PCIe reset
Reference clock request signal
Wireless disable 2
PCIe wake
Wireless disable 1
Ground
Ground
CNVi*
Signal
Description
Key
Key
Key
Key
Key
Key
Key
RGI_DT
RGI bus Tx
GND
Ground
RGI_RSP
RGI bus Rx
-
BRI_DT
BRI bus Tx
-
-
GND
Ground
-
-
-
-
-
GND
Ground
-
-
-
-
USUCLK
32.768 kHz clock supply input
GND
Ground
-
-
W_DISABLE2#
Wireless disable 2
-
W_DISABLE1#
Wireless disable 1
GND
Ground
-
WT_D1N
CNVio bus Tx Lane 1 (-)
-
WT_D1P
CNVio bus Tx Lane 1 (+)
-
GND
Ground
REFCLK0
Reference clock
WT_D0N
CNVio bus Tx Lane 0 (-)
MITX-CFL0 Series - User Guide, Rev. 1.1
Note
// 54
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