Akd Synqnet I/O Mapping; General Purpose I/O - Kollmorgen AKD-x00306 Manual

AKD SynqNet | 6 AKD SynqNet I/O Mapping

6 AKD SynqNet I/O Mapping

The following tables show the mapping from AKD physical pin names to SynqNet logical names.
These tables show mapping for FPGAs, version 0200_00_02 and later.

6.1 General Purpose I/O

AKD Firmware AKD Connector
DIN1.STATE X7-10
DIN2.STATE X7-9
DIN3.STATE X7-4
DIN4.STATE X7-3
DIN5.STATE X8-6
DIN6.STATE X8-5
DIN7.STATE X7-2
DIN9.STATE X9-1/2
DIO9.STATE
DIN10.STATE X9-4/5
DIO10.STATE
DIN11.STATE X7-7/8
DIO11.STATE
DOUT1.STATE X7-8/7
DOUT2.STATE X7-6/5
NA X10-6/7
Notes:
The RS485 outputs must be enabled using AKD-SQ parameters.
l
Set DRV.EMUMODE = 10 (fieldbus) for SynqNet gpio output mode.
l
Set DIO9.DIR=1, DIO10.DIR=1, DIO11.DIR=1 to enable individual outputs.
l
GPIO input "Analog Z Pulse" not supported on AKD Rev 7 control boards (AKD-SQ prototypes only).
l
18 Kollmorgen | kdn.kollmorgen.com | October 2020
AKD Pin SynqNet MPI Name
Name
Digital Input GPIO input "DIN 1 (HS)"
1
Digital Input GPIO input "DIN 2 (HS)"
2
Digital Input GPIO input "DIN 3"
3
Digital Input GPIO input "DIN 4"
4
Digital Input GPIO input "DIN 5"
5
Digital Input GPIO input "DIN 6"
6
Digital Input GPIO input "DIN 7"
7
Emulated GPIO bidir "RS485 IO 1"
Encoder A
Emulated GPIO bidir "RS485 IO 2"
Encoder A
Emulated GPIO bidir "RS485 IO 3"
Encoder
Zero
Digital Out- GPIO output "DOUT1"
put 1
Digital Out- GPIO output "DOUT1"
put 2
Zero GPIO input "Analog Z
Pulse"
Notes
High speed opto input.
Also maps to HOME.
High speed opto input.
Also maps to "LIMIT_
HW_POS".
Also maps to "LIMIT_
HW_NEG".
See note to enable out-
put.
See note to enable out-
put.
See note to enable out-
put. Also maps to
"INDEX_
SECONDARY."
Also maps to "INDEX_
PRIMARY." Some
encoder types do not
use index pin.