Configuration Jumpers - Epson S5U13705B00C User Manual

3.2 Configuration Jumpers

Jumper Function
JP1 IOVDD Selection
JP2 Bus Clock Selection
JP3 BS# Signal Selection
JP4 LCD Panel Voltage Selection
JP5 PCI Bridge FPGA
JP6 LCDPWR Polarity
JP7 CLKI Selection
= Required settings when used with PCI Bridge FPGA
Note
S5U13705B00C Rev 2.0 PCI Evaluation Board
Rev. 3.1
The S5U13705B00C has six jumper blocks which configure various setting on the board.
The jumper positions for each function are shown below.
Table 3-2: Jumper Summary
Position 1-2
+3.3V IOVDD
External Oscillator (U7)
Pulled Down to GND (for
Generic #1 Interface)
+3.3V LCDVCC
Disabled for non-PCI host
Active Low
External Oscillator (U2)
JP1 - IOVDD Selection
JP1 selects the IOVDD voltage for S1D13705.
When the jumper is in position 1-2, IOVDD is 3.3V. This settings must be used for a 3.3V
host CPU system.
When the jumper is in position 2-3, IOVDD is 5.0V. This setting must be used for a 5.0V
host CPU system.
For PCI host, JP1 can be set in either position.
Figure 3-2: Configuration Jumper (JP1) Location
Seiko Epson Corporation
Installation and Configuration
Position 2-3
+5.0V IOVDD
From Host CPU
Pulled High to IOVDD (for
Generic #2 Interface)
+5.0V LCDVCC
n/a
Active High
BCLK
JP1
3.3 Volt
5.0 Volt
IOVDD
IOVDD
No Jumper
n/a
n/a
For SH-3, SH-4, MC68k #1
and MC68K #2 bus
n/a
Enabled for PCI host
n/a
n/a
9