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Epson S5U13705B00C User Manual

S1d13705 embedded memory lcd controller
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S1D13705 Embedded Memory LCD Controller
S5U13705B00C Rev. 2.0
Evaluation Board User Manual
Document Number: X27A-G-014-03.1
Rev. 3.1

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Summary of Contents for Epson S5U13705B00C

  • Page 1 S1D13705 Embedded Memory LCD Controller S5U13705B00C Rev. 2.0 Evaluation Board User Manual Document Number: X27A-G-014-03.1 Rev. 3.1...
  • Page 2 This evaluation board/kit or development tool is intended for use by an electronics engineer and is not a consumer product. The user should use it properly and in a safe manner. Seiko Epson does not assume any responsibility or liability of any kind of damage and/or fire caused by the use of it.

  • Page 3: Table Of Contents

    12 Sales and Technical Support ......30 Seiko Epson Corporation S5U13705B00C Rev 2.0 PCI Evaluation Board Rev. 3.1...
  • Page 4 THIS PAGE LEFT BLANK Seiko Epson Corporation S5U13705B00C Rev 2.0 PCI Evaluation Board Rev. 3.1...

  • Page 5: Introduction

    Introduction 1 Introduction This manual describes the setup and operation of the S5U13705B00C Rev. 2.0 Evaluation Board. The board is designed as an evaluation platform for the S1D13705 Embedded Memory LCD Controller. This document is updated as appropriate. Please check for the latest revision of this document before beginning any development.

  • Page 6: Features

    Features 2 Features Following are some features of the S5U13705B00C Rev. 2.0 Evaluation Board: • 80-pin TQFP S1D13705F00A Embedded Memory LCD Controller with 80K bytes of embedded SRAM. • Headers for connecting to various Host Bus Interfaces. • Configuration options.

  • Page 7: Installation And Configuration

    Installation and Configuration 3 Installation and Configuration The S5U13705B00C is designed to support as many platforms as possible. The S5U13705B00C incorporates a DIP switch and seven jumpers which allow both evaluation board and S1D13705 LCD controller to be configured for a specified evaluation platform.
  • Page 8 GPIO0 Hardware Suspend Enable Hardware Suspend Disable = Required settings when used with PCI Bridge FPGA Note The selection between Generic #1 and Generic #2 is made with JP3. Seiko Epson Corporation S5U13705B00C Rev 2.0 PCI Evaluation Board Rev. 3.1...

  • Page 9: Configuration Jumpers

    Installation and Configuration 3.2 Configuration Jumpers The S5U13705B00C has six jumper blocks which configure various setting on the board. The jumper positions for each function are shown below. Table 3-2: Jumper Summary Jumper Function Position 1-2 Position 2-3 No Jumper IOVDD Selection +3.3V IOVDD...
  • Page 10 For SH-3, SH-4, MC68K #1 and MC68K #2 buses, which use BS# line, the jumper should not be installed. Pulled High Pulled Low Figure 3-4: Configuration Jumper (JP3) Location Seiko Epson Corporation S5U13705B00C Rev 2.0 PCI Evaluation Board Rev. 3.1...
  • Page 11 When the jumper is off, the PCI bridge FPGA is enabled. The jumper must not be present for PCI host. FPGA FPGA Enabled Disabled Figure 3-6: Configuration Jumper (JP5) Location Seiko Epson Corporation S5U13705B00C Rev 2.0 PCI Evaluation Board Rev. 3.1...
  • Page 12 When the jumper is in position 1-2, CLKI signal is provided by external oscillator U2 When the jumper is in position 2-3, CLKI signal is the same as BCLK signal CLKI External Same as Oscillator (U2) BCLK Figure 3-8: Configuration Jumper (JP7) Location Seiko Epson Corporation S5U13705B00C Rev 2.0 PCI Evaluation Board Rev. 3.1...

  • Page 13: Cpu Interface

    WAIT# WAIT# WAIT# RDY# DTACK# DSACK1# RESET# RESET# RESET# RESET# RESET# RESET# RESET# Note If the target MC68K bus is 32-bit, then these signals should be connected to D[31:16]. Seiko Epson Corporation S5U13705B00C Rev 2.0 PCI Evaluation Board Rev. 3.1...

  • Page 14: Cpu Bus Connector Pin Mapping

    Connected to WE0# of the S1D13705 Connected to WAIT# of the S1D13705 Connected to CS# of the S1D13705 Not connected Connected to WE1# of the S1D13705 Connected to IOVDD Seiko Epson Corporation S5U13705B00C Rev 2.0 PCI Evaluation Board Rev. 3.1...
  • Page 15 +5 volt supply Connected to RD/WR# of the S1D13705 Connected to BS# of the S1D13705 Connected to BCLK of the S1D13705 Connected to RD# of the S1D13705 Not connected Not connected Seiko Epson Corporation S5U13705B00C Rev 2.0 PCI Evaluation Board Rev. 3.1...

  • Page 16: Lcd Interface Pin Mapping

    FPSHIFT. For further FPDATxx to LCD interface mapping, see S1D13705 Hardware Functional Specification, document number X27A-A-001-xx. LCDPWR on J5 can be inverted by setting JP6 to 1-2. Seiko Epson Corporation S5U13705B00C Rev 2.0 PCI Evaluation Board Rev. 3.1...

  • Page 17: Technical Description

    6.2 Direct Host Bus Interface Support The S5U13705B00C is specifically designed to work using the PCI Bridge FPGA in a standard PCI bus environment. However, the S1D13705 directly supports many other host bus interfaces. Connectors H1 and H2 provide the necessary IO pins to interface to these host buses.

  • Page 18: Adjustable Lcd Panel Negative Power Supply (Vlcd)

    REG[02h] bit1 to 1 and then can be activated by DIP switch SW1-6. See Table 3-1: “Configuration DIP Switch Settings” on page 8. Seiko Epson Corporation S5U13705B00C Rev 2.0 PCI Evaluation Board Rev. 3.1...

  • Page 19: Clock Options

    BCLK and CLKI. The bus clock (BCLK) is selectable and can be provided by a 50MHz oscillator (U7, socketed) or the host CPU (for non-PCI host). Seiko Epson Corporation S5U13705B00C Rev 2.0 PCI Evaluation Board Rev. 3.1...

  • Page 20: Software

    OEM for different panel types, resolutions and color depths only by modifying the source. The S1D13705 test utilities and drivers are available from your sales support contact or on the internet at vdc.epson.com. Seiko Epson Corporation S5U13705B00C Rev 2.0 PCI Evaluation Board Rev. 3.1...

  • Page 21: Parts List

    Machined socket, 14-pin Fox 6.0MHz oscillator or equiv., 14-pin 6MHz DIP pckg, socketed U3,U4,U5 74AHC244 SO-22, TI74AHC244 or equivalent Linear Technology 5V to 3.3V LT1117CM-3.3 regulator, 800mA or equiv. Seiko Epson Corporation S5U13705B00C Rev 2.0 PCI Evaluation Board Rev. 3.1...
  • Page 22 Machined socket, 8-pin EPC1441PC8 Altera EPC1441PC8, socketed JP1,JP2,JP3,JP4,JP6,J Jumper shunt for 0.1" header Computer Bracket, Blank - PCI, Bracket Keystone - Cat. No. 9203 Scew Pan Head, #4-40 x 1/4" Seiko Epson Corporation S5U13705B00C Rev 2.0 PCI Evaluation Board Rev. 3.1...

  • Page 23: Schematics

    Schematics 9 Schematics Figure 9-1: S1D13705B00C Schematics (1 of 5) Seiko Epson Corporation S5U13705B00C Rev 2.0 PCI Evaluation Board Rev. 3.1...
  • Page 24 Schematics Figure 9-2: S1D13705B00C Schematics (2 of 5) Seiko Epson Corporation S5U13705B00C Rev 2.0 PCI Evaluation Board Rev. 3.1...
  • Page 25 Schematics Figure 9-3: S1D13705B00C Schematics (3 of 5) Seiko Epson Corporation S5U13705B00C Rev 2.0 PCI Evaluation Board Rev. 3.1...
  • Page 26 Schematics Figure 9-4: S1D13705B00C Schematics (4 of 5) Seiko Epson Corporation S5U13705B00C Rev 2.0 PCI Evaluation Board Rev. 3.1...
  • Page 27 Schematics Figure 9-5: S1D13705B00C Schematics (5 of 5) Seiko Epson Corporation S5U13705B00C Rev 2.0 PCI Evaluation Board Rev. 3.1...

  • Page 28: Board Layout

    Board Layout 10 Board Layout Seiko Epson Corporation S5U13705B00C Rev 2.0 PCI Evaluation Board Rev. 3.1...

  • Page 29: Change Record

    Change Record 11 Change Record X27A-G-014-03 Revision 3.1 - Issued: March 26, 2018 • updated Sales and Technical Support Section • updated some formatting Seiko Epson Corporation S5U13705B00C Rev 2.0 PCI Evaluation Board Rev. 3.1...

  • Page 30: Sales And Technical Support

    Sales and Technical Support 12 Sales and Technical Support For more information on Epson Display Controllers, visit the Epson Global website. https://global.epson.com/products_and_drivers/semicon/products/display_controllers/ For Sales and Technical Support, contact the Epson representative for your region. https://global.epson.com/products_and_drivers/semicon/information/support.html Seiko Epson Corporation S5U13705B00C Rev 2.0 PCI Evaluation Board...

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