Configuration Jumpers - Epson S5U13506P00C100 User Manual

Epson Research and Development
Vancouver Design Center

3.2 Configuration Jumpers

Jumper Function
JP1 BUSCLK Selection
JP2 CLKI Selection
JP3 VDD current
JP4 DACVDD current
JP5 LCD Panel Voltage
JP6 Panel Enable Polarity
JP7 PCI FPGA enable
JP8 IREF for CRT/TV DAC
Note
S5U13506P00C100 PCI Evaluation Board User Manual
Issue Date: 2009/03/02
The S5U13505B00C has seven jumper blocks which configure various board settings. The
jumper positions for each function are shown below.
Table 3-3: Jumper Settings
Position 1-2
BUSCLK from U2 oscillator
CLKI from U3 oscillator
Normal operation
Normal operation
+5V LCDVCC
LCDPWR active high
Disable FPGA for non-PCI
host
4.6mA for CRT
= Default configuration
JP1 - BUSCLK Selection
JP1 selects the source for BUSCLK.
When the jumper is at position 1-2, the BUSCLK source is provided by the oscillator at U2
(default setting).
When the jumper is at position 2-3, the BUSCLK source is provided by the non-PCI host
system.
When used in a PCI environment, JP1 must be set to the 1-2 position.
Figure 3-2: Configuration Jumper (JP1) Location
Position 2-3
BUSCLK from H2 header
CLKI is the same as BUSCLK
n/a
n/a
+3.3V LCDVCC
LCDPWR active low
n/a
9.2mA for TV
JP1
BUSCLK from
Oscillator (U2)
Jumper Off
n/a
n/a
Current measurement for
VDD
Current measurement for
DACVDD
n/a
n/a
Enable FPGA for PCI host
n/a
BUSCLK
from H2
S1D13506
X25B-G-014-02
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