Cpu Interface; Cpu Interface Pin Mapping - Epson S5U13705B00C User Manual

S1d13705 embedded memory lcd controller
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4 CPU Interface

4.1 CPU Interface Pin Mapping

S1D13705
Generic #1
Pin Name
AB[16:1]
A[16:1]
AB0
A0
DB[15:0]
D[15:0]
CS#
BCLK
BCLK
BS#
Connect to VSS
RD/WR#
RD1#
RD#
RD0#
WE0#
WE0#
WE1#
WE1#
WAIT#
WAIT#
RESET#
RESET#
Note
S5U13705B00C Rev 2.0 PCI Evaluation Board
Rev. 3.1
Table 4-1: CPU Interface Pin Mapping
Generic #2
A[16:1]
A0
D[15:0]
External Decode
BCLK
Connect to IOVDD
Connect to IOVDD
RD#
WE#
BHE#
WAIT#
RESET#
1
If the target MC68K bus is 32-bit, then these signals should be connected to D[31:16].
Seiko Epson Corporation
Hitachi SH-3 Hitachi SH-4
A[16:1]
A[16:1]
A0
A0
D[15:0]
D[15:0]
CSn#
CSn#
CKIO
CKIO
BS#
BS#
RD/WR#
RD/WR#
RD#
RD#
WE0#
WE0#
WE1#
WE1#
WAIT#
RDY#
RESET#
RESET#
CPU Interface
Motorola
Motorola
MC68K #1
MC68K #2
A[16:1]
A[16:1]
LDS#
D[15:0]
D[15:0]
External Decode
CLK
CLK
AS#
AS#
R/W#
R/W#
Connect to IOVDD
SIZ1
Connect to IOVDD
SIZ0
UDS#
DS#
DTACK#
DSACK1#
RESET#
RESET#
A0
1
13

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