Lcd Interface Pin Mapping - Epson S5U13705B00C User Manual

LCD Interface Pin Mapping

5 LCD Interface Pin Mapping
Connector Pin
Pin Name
No.
BFPDAT0 1
BFPDAT1 3
BFPDAT2 5
BFPDAT3 7
BFPDAT4 9
BFPDAT5 11
BFPDAT6 13
BFPDAT7 15
BFPDAT8 17
BFPDAT9 19
BFPDAT10 21
BFPDAT11 23
BFPSHIFT 33
BDRDY 35 & 38
BFPLINE 37
BFPFRAME 39
GND 2-26 (Even Pins)
VLCD 30
LCDVCC 32
+12V 34
VDDH 36
BLCDPWR 40
16
Table 5-1: LCD Signal Connector (J5)
Monochrome Passive
Single
4-bit 8-bit
driven 0 D0
driven 0 D1
driven 0 D2
driven 0 D3
D0 D4
D1 D5
D2 D6
D3 D7
MOD
LCDPWR
Note
1
These pin mappings use signal names commonly used for each panel type, however
signal names may differ between panel manufacturers. The values shown in brackets
represent the color components as mapped to the corresponding FPDATxx signals at
the first valid edge of FPSHIFT. For further FPDATxx to LCD interface mapping, see
S1D13705 Hardware Functional Specification, document number X27A-A-001-xx.
2
LCDPWR on J5 can be inverted by setting JP6 to 1-2.
Seiko Epson Corporation
Color Passive Panel
Single
Dual
Format 1 Format 2
8-bit 4-bit 8-bit
1
LD0 driven 0 D0 (B5)
1
LD1 driven 0 D1 (R5)
1
LD2 driven 0 D2 (G4)
1
LD3 driven 0 D3 (B3)
1 1
UD0 D0 (R2) D4 (R3)
1 1
UD1 D1 (B1) D5 (G2)
1 1
UD2 D2 (G1) D6 (B1)
1 1
UD3 D3 (R1) D7 (R1)
GPIO1
GPIO2
GPIO3
GPIO4
FPSHIFT
FPSHIFT2
FPLINE
FPFRAME
GND
Adjustable -24V to -14V negative LCD bias
LCDVCC (3.3V / 5.0V)
+12V
Adjustable +23V to +40V positive LCD bias
2
(for controlling on-board LCD bias power supply on/off)
Color TFT Panel
Dual
8-bit 8-Bit 9-bit
1 1
D0 (G3) LD0 (lR2) R2
1 1
D1 (R3) LD1 (lB1) R1
1 1
D2 (B2) LD2 (lG1) R0
1 1
D3 (G2) LD3 (lR1) G2
1 1
D4 (R2) UD0 (uR2) G1
1 1
D5 (B1) UD1 (uB1) G0
1 1
D6 (G1) UD2 (uG1) B2
1 1
D7 (R1) UD3 (uR1) B1
B0
MOD
S5U13705B00C Rev 2.0 PCI Evaluation Board
12-bit
R3
R2
R1
G3
G2
G1
B3
B2
B1
R0
G0
B0
DRDY
Rev. 3.1