Table of Contents
Advertisement
Installation and Configuration
S1D13705
Switch
Signal
SW1-[3:1]
CNF[2:0]
SW1-4
CNF3
SW1-5
Not Used
SW1-6
GPIO0
= Required settings when used with PCI Bridge FPGA
8
The S1D13705 has 4 configuration inputs (CONF[3:0]) and BS# input, which are read on
the rising edge of RESET#. All S1D13705 configuration inputs and BS# input are fully
configurable using a six position DIP switch as described below and a jumper for BS#.
Table 3-1: Configuration DIP Switch Settings
Value on this pin at rising edge of RESET# is used to configure:
Open (Off/1)
Select host bus interface as follows:
CNF2
CNF1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Note: The host bus interface is 16-bit.
Big Endian bus interface
Not Used
Hardware Suspend Enable
Note
1
The selection between Generic #1 and Generic #2 is made with JP3.
Seiko Epson Corporation
CNF0
Host Bus Interface
0
SH-4
1
SH-3
0
Reserved
1
MC68K #1
0
Reserved
1
MC68K #2
0
Reserved
1
Generic #1/Generic #2
Little Endian bus interface
Hardware Suspend Disable
S5U13705B00C Rev 2.0 PCI Evaluation Board
Closed (On/0)
1
Rev. 3.1
Advertisement
Table of Contents
