Cpu Interface Pin Mapping - Epson S5U13506P00C100 User Manual

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4.2.1 CPU Interface Pin Mapping

S1D13505
Hitachi
Pin Generic
SH-4/SH-3
Names
AB20 A20
AB19 A19
AB18 A18
AB17 A17
AB[16:13] A[16:13] A[16:13]
AB[12:1] A[12:1] A[12:1]
1
AB0 A0
DB[15:8] D[15:0] D[15:8]
DB[7:0] D[7:0] D[7:0]
WE1# WE1# WE1#
M/R#
CS#
BUSCLK BCLK CKIO
Connected
BS#
to V
DD
RD/WR# RD1# RD/WR#
RD# RD0#
WE0# WE0# WE0#
RDY#
WAIT# WAIT#
/WAIT#
RESET# RESET# RESET#
Note
S5U13506P00C100 PCI Evaluation Board User Manual
Issue Date: 2009/03/02
The functions of the S1D13506 host interface pins are mapped to each host bus interface
according to the following table.
Table 4-4: CPU Interface Pin Mapping
Motorola
MIPS/ISA MC68K
Bus 1
A20 LatchA20 A20
A19 SA19 A19
A18 SA18 A18
A17 SA17 A17
SA[16:13] A[16:13]
SA[12:1] A[12:1]
1
A0 SA0 LDS#
SD[15:0] D[15:8]
SD[7:0] D[7:0]
SBHE# UDS#
External Decode
External Decode
CLK CLK
Connected to
BS# AS#
V
DD
Connected to
R/W#
V
DD
Connected
RD# MEMR#
to V
Connected
MEMW#
to V
IOCHRDY DTACK# DSACK1#
inverted
RESET#
RESET
1
A0 for these busses is not used internally by the S1D13506.
Motorola
Motorola
MC68K
PowerPC
Bus 2
A20 A11
A19 A12
A18 A13
A17 A14
A[16:13] A[15:18]
A[12:1] A[19:30]
A0 A31
D[31:24] D[0:7]
D[23:16] D[8:15]
DS# BI
CLK CLKOUT
AS# TS
R/W# RD/WR
SIZ1 TSIZ0
DD
SIZ0 TSIZ1
DD
TA
RESET# RESET#
Philips
PC Card PR31500
/PR31700
A20 ALE
A19 /CARDREG
A18 /CARDIORD
A17 /CARDIOWR
A[16:13] Connected to V
A[12:1] A[12:1]
1
A0 A0
D[15:0] D[23:16]
D[7:0] D[31:24]
-CE2 /CARDxCSH
Connected to V
Connected to V
CLK DCLKOUT
Connected
Connected to V
to V
DD
-CE1 /CARDxCSL
-OE /RD
-WE /WE
-WAIT /CARDxWAIT CARDxWAIT*
inverted
RESET#
RESET
Page 15
Toshiba
TX3912
ALE
CARDREG*
CARDIORD*
CARDIOWR*
DD
A[12:1]
A0
D[23:16]
D[31:24]
CARDxCSH*
DD
DD
DCLKOUT
DD
CARDxCSL*
RD*
WE*
PON*
S1D13506
X25B-G-014-02