Cpu Interface; Cpu Interface Pin Mapping - Epson S5U13A04B00C User Manual

CPU Interface

4 CPU Interface

4.1 CPU Interface Pin Mapping

S1D13A04 Pin Name
AB[17:1]
AB0
DB[15:0]
CS#
M/R#
CLKI
BS#
RD/WR#
RD#
WE0#
WE1#
WAIT#
RESET#
Note
12
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Table 4-1: CPU Interface Pin Mapping
Generic #1 Generic #2
SH-3 /SH-4
A[17:1] A[17:1]
1
A0 A0
D[15:0] D[15:0]
External Decode
BUSCLK BUSCLK
3
Connected to HIOV
DD
Connected
RD1#
3
to HIOV
DD
RD0# RD#
WE0# WE#
WE1# BHE#
WAIT# WAIT#
RESET# RESET#
1
A0 for these busses is not used internally by the S1D13A04 and should be connected
to V .
SS
2
If the target MC68K bus is 32-bit, then these signals should be connected to D[31:16].
3
These pins are not used in their corresponding host interface mode. Systems are
responsible for externally connecting them to Host Interface IO V
Seiko Epson Corporation
Hitachi Motorola Motorola
MC68K #1 MC68K #2
A[17:1] A[17:1] A[17:1]
1
A0 LDS#
D[15:0] D[15:0] D[15:0]
CSn# External Decode
External Decode
CKIO CLK
BS# AS#
RD/WR# R/W#
Connected
RD#
3
to HIOV
DD
Connected
WE0#
3
to HIOV
DD
WE1# UDS#
WAIT#/
DTACK# DSACK1#
RDY#
RESET# RESET# RESET#
Motorola MC68EZ328/
REDCAP2 MC68VZ328
DragonBall
A[17:1]
1
A0 A0
2
D[15:0]
CSn
CLK CLK
AS# Connected to HIOV
Connected to
R/W# R/W
SIZ1 OE
SIZ0 EB1
DS# EB0
N/A
RESET_OUT
.
DD
S5U13A04B00C Rev 1.0 Evaluation Board
Motorola
A[17:1]
1
A0
D[15:0]
CSX
CLK
3
DD
3
HIOV
DD
OE
LWE
UWE
DTACK
RESET
Rev. 3.1