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4 CPU Interface
4.1 CPU Interface Pin Mapping
S1D13A05
Generic #1
Pin Name
AB[17:1]
A[17:1]
1
AB0
A0
DB[15:0]
D[15:0]
CS#
External Decode
M/R#
CLKI
BUSCLK
BS#
Connected to IOV
RD/WR#
RD1#
RD#
RD0#
WE0#
WE0#
WE1#
WE1#
WAIT#
WAIT#
RESET#
RESET#
Note
S5U13A05B00C Rev 1.0 Evaluation Board
Rev. 1.1
All manuals and user guides at all-guides.com
Table 4-1: Host Bus Interface Pin Mapping
Hitachi
Generic #2
SH-3/SH-4
A[17:1]
A[17:1]
1
A0
A0
D[15:0]
D[15:0]
CSn#
BUSCLK
CKIO
3
BS#
DD
Connected to
RD/WR#
3
IOV
DD
RD#
RD#
WE#
WE0#
BHE#
WE1#
WAIT#/
WAIT#
RDY#
RESET#
RESET#
1
A0 for these bus interfaces is not used internally by the S1D13A05 and should be
connected to V
.
SS
2
If the target MC68K bus is 32-bit, then these signals should be connected to D[31:16].
3
These pins are not used in their corresponding host interface mode. Systems are
responsible for externally connecting them to IO V
Seiko Epson Corporation
Motorola
Motorola
MC68K #1
MC68K #2
A[17:1]
A[17:1]
LDS#
A0
2
D[15:0]
D[15:0]
External Decode
External Decode
CLK
CLK
AS#
AS#
R/W#
R/W#
Connected to
SIZ1
3
IOV
DD
Connected to
SIZ0
3
IOV
DD
UDS#
DS#
DTACK#
DSACK1#
RESET#
RESET#
DD
CPU Interface
Motorola
Motorola
MC68EZ328/
REDCAP2
MC68VZ328
DragonBall
A[17:1]
A[17:1]
1
A0
A0
D[15:0]
D[15:0]
CSn
CSX
CLK
CLKO
Connected to IOV
DD
Connected to
R/W
IOV
OE
OE
EB1
LWE
EB0
UWE
N/A
DTACK
RESET_OUT
RESET
.
1
3
3
DD
13
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