Cpu Interface; Cpu Interface Pin Mapping - Epson S5U13706P00C100 User Manual

Epson Research and Development
Vancouver Design Center

4 CPU Interface

4.1 CPU Interface Pin Mapping

S1D13706
Generic #1
Pin Name
AB[16:1] A[16:1]
1
AB0 A0
DB[15:0] D[15:0]
CS# External Decode
M/R#
CLKI BUSCLK
BS# Connected to V
RD/WR# RD1#
RD# RD0#
WE0# WE0#
WE1# WE1#
WAIT# WAIT#
RESET# RESET#
Note
S5U13706P00C100 Evaluation Board User Manual
Issue Date: 2009/03/03
Table 4-1: CPU Interface Pin Mapping
Hitachi
Generic #2
SH-3 /SH-4
A[16:1] A[16:1]
1
A0 A0
D[15:0] D[15:0]
CSn#
BUSCLK CKIO
3
BS#
DD
Connected to
RD/WR#
3
V
DD
RD# RD#
WE# WE0#
BHE# WE1#
WAIT#/
WAIT#
RDY#
RESET# RESET#
1
A0 for these busses is not used internally by the S1D13706.
2
If the target MC68K bus is 32-bit, then these signals should be connected to D[31:16].
3
These pins are not used in their corresponding Host Bus Interface mode. Systems are
responsible for externally connecting them to the host interface IO V
Motorola Motorola
MC68K #1 MC68K #2
A[16:1] A[16:1]
LDS#
D[15:0] D[15:0]
External Decode
External Decode
CLK
AS#
R/W# R/W#
Connected to
3
V
DD
Connected to
3
V
DD
UDS#
DTACK# DSACK1#
RESET# RESET#
Revision 1.1
Motorola
REDCAP2
A[16:1]
1
A0 A0
2
D[15:0]
CSn#
CLK CLK
AS# Connected to V
R/W#
SIZ1 OE#
SIZ0 EB1#
DS# EB0#
N/A
RESET#
.
DD
Page 11
Motorola
MC68EZ328/
MC68VZ328
DragonBall
A[16:1]
1
A0
D[15:0]
CSA#
CLK
3
DD
Connected to
3
V
DD
OE#
LWE#
UWE#
DTACK#
RESET#
S1D13706
X31B-G-021-01