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3.5.3.3 CPU & PCI Bus Control
Item
PCI Master 0 WS Write
PCI Delay Transaction
VLink Mode Selection
VLink 8X Support
DRDY_Timing
3.5.3.4 Memory Hole
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved it cannot be cached. The user information of peripherals that need to use this area
of system memory usually2 discussed their memory requirements.
The choices: Disabled, 15M-16M.
Options
Enabled
To write PCI bus while zero wait state is executed.
Disabled
This feature is used to meet the latency of PCI cycles to
and from the ISA bus. The ISA bus is much, much slower
than the PCI bus. Thus, PCI cycles to and from the ISA
bus take a longer time to complete and this slows the PCI
bus down.
However, enabling PCI Delayed Transaction enables
the chipset's embedded 32-bit posted write buffer to
Enabled
support delayed transaction cycles. This means that
Disabled
transactions to and from the ISA bus are buffered and the
PCI bus can be freed to perform other transactions while
the ISA transaction is underway.
This option should be enabled for better performance
and to meet PCI 2.1 specifications. "Disabled" is set only
if the PCI cards cannot work properly or if an ISA card
that is not PCI 2.1 compliant is used.
By Auto
Mode 0
The North Bridge interface to the South Bridge through a
Mode 1
high speed(up to 1GB/Sec)8x, 66MHz Data Transfer
Mode 2
interconnect bus caller "V-Link". This item allows you to
Mode 3
select the V-Link mode from 0 to 4.
Mode 4
Enabled
The feature is to toggle the V-Link bus mode between the
Disabled
original V-Link and the newer and faster 8X V-Link.
Slowest
Allows to set the timing for each cycle that data is
Default
transferred.
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Description
ECM-CX700 Series User's Manual 65
User's Manual
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