Atmel SAM L22G Manual
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Atmel SAM L22G Manual

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Table of Contents

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Introduction

®
Atmel
| SMART SAM L22 is a series of Ultra low-power segment LCD
microcontrollers using the 32-bit ARM
48- to 100-pins with up to 256KB Flash and 32KB of SRAM and to drive up
to 320 LCD segments. The SAM L22 devices operate at a maximum
frequency of 32MHz and reach 2.46 CoreMark
power management technologies the SAM L22 devices run down to
39µA/MHz (CPU running CoreMark) in active mode and down to 490nA in
ultra low-power backup mode with RTC.

Features

•
Processor
–
ARM Cortex-M0+ CPU running at up to 32MHz
•
Single-cycle hardware multiplier
•
Micro Trace Buffer
•
Memory Protection Unit (MPU)
•
Memories
–
64/128/256KB in-system self-programmable Flash
–
2/4/8KB Flash Read-While-Write section
–
8/16/32KB SRAM Main Memory
•
System
–
Power-on reset (POR) and programmable brown-out detection
(BOD)
–
Internal and external clock options
–
External Interrupt Controller (EIC)
•
16 external interrupts that can use any I/O-Pin
•
One non-maskable interrupt on one I/O-Pin
–
Two-pin Serial Wire Debug (SWD)
•
Low Power
–
Idle, Standby, Backup, and Off sleep modes
–
SleepWalking peripherals
SMART ARM-based Microcontrollers
SAM L22G / L22J / L22N
DATASHEET COMPLETE
®
®
Cortex
-M0+ processor, ranging from
®
/MHz. With sophisticated
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016

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Summary of Contents for Atmel SAM L22G

  • Page 1: Introduction

    SMART ARM-based Microcontrollers SAM L22G / L22J / L22N DATASHEET COMPLETE Introduction ® Atmel | SMART SAM L22 is a series of Ultra low-power segment LCD ® ® microcontrollers using the 32-bit ARM Cortex -M0+ processor, ranging from 48- to 100-pins with up to 256KB Flash and 32KB of SRAM and to drive up to 320 LCD segments.
  • Page 2 USART with full-duplex and single-wire half-duplex configuration • ISO7816 • C up to 3.4MHz • – One AES encryption engine Max 1 high-speed mode and max 3 fast mode I Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 3 • Packages – 100-pin TQFP – 64-pin TQFP, QFN – 49-pin WLCSP – 48-pin TQFP, QFN • Operating Voltage – 1.62V – 3.63V except the VLCD Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 4: Table Of Contents

    10.3. NVM User Row Mapping......................40 10.4. NVM Software Calibration Area Mapping...................41 10.5. Serial Number..........................41 11. Processor and Architecture..................42 11.1. Cortex M0+ Processor........................42 11.2. Nested Vector Interrupt Controller....................44 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 5 16.3. Block Diagram.......................... 121 16.4. Signal Description........................122 16.5. Product Dependencies......................122 16.6. Functional Description......................123 16.7. Register Summary........................129 16.8. Register Description......................... 132 17. MCLK – Main Clock....................141 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 6 21.1. Overview...........................207 21.2. Features........................... 207 21.3. Block Diagram.......................... 208 21.4. Signal Description........................208 21.5. Product Dependencies......................208 21.6. Functional Description......................209 21.7. Register Summary........................222 21.8. Register Description......................... 223 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 7 25.11. Register Summary - CLOCK....................403 25.12. Register Description - CLOCK....................405 26. DMAC – Direct Memory Access Controller............432 26.1. Overview...........................432 26.2. Features........................... 432 26.3. Block Diagram.......................... 434 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 8 30.3. Block Diagram.......................... 570 30.4. Signal Description........................571 30.5. Product Dependencies......................571 30.6. Functional Description......................572 30.7. Register Summary........................576 30.8. Register Description......................... 577 31. SERCOM – Serial Communication Interface............592 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 9 35.1. Overview...........................743 35.2. Features........................... 743 35.3. Block Diagram.......................... 744 35.4. Signal Description........................744 35.5. Product Dependencies......................745 35.6. Functional Description......................746 35.7. Register Summary........................761 35.8. Register Description......................... 765 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 10 40. CCL – Configurable Custom Logic................ 970 40.1. Overview...........................970 40.2. Features........................... 970 40.3. Block Diagram.......................... 971 40.4. Signal Description........................971 40.5. Product Dependencies......................971 40.6. Functional Description......................972 40.7. Register Summary........................983 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 11 45.3. General Operating Ratings ....................1147 45.4. Supply Characteristics ......................1148 45.5. Maximum Clock Frequencies ....................1149 45.6. Power Consumption ......................1150 45.7. Wake-up Timing........................1154 45.8. IO Pin Characteristics......................1155 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 12 52. Datasheet Revision History................. 1223 52.1. Rev.E - 07/2016........................1223 52.2. Rev.D - 05/2016........................1223 52.3. Rev.C - 01/2016........................1226 52.4. Rev.B - 11/2015........................1227 52.5. Rev A - 08/2015........................1229 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 13: Description

    Description Atmel | SMART SAM L22 is a series of Ultra low-power segment LCD microcontrollers using the 32-bit ® ® Cortex -M0+ processor, ranging from 48- to 100-pins with up to 256KB Flash and 32KB of SRAM and can drive up to 320 LCD segments. The SAM L22 devices operate at a maximum frequency of 32MHz and reach 2.46 Coremark/MHz.

  • Page 14: Configuration Summary

    True Random Generator (TRNG) Serial Communication Interface (SERCOM) instances Analog-to-Digital Converter (ADC) channels Two Analog Comparators (AC) with number of external input channels Tamper Input Pins Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 15 The number of Y-lines depends on the configuration of the device, as some I/O lines can be configured as either X-lines or Y-lines. The number given here is the maximum number of Y-lines that can be obtained. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 16: Ordering Information

    Table 3-2. SAM L22J Ordering Codes Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type ATSAML22J16A-AUT TQFP64 Tape & Reel ATSAML22J16A-MUT QFN64 ATSAML22J17A-AUT 128K TQFP64 Tape & Reel ATSAML22J17A-MUT QFN64 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 17: Sam L22G

    DID=0x10820xxx, with the last digits identifying the variant: Table 3-4. SAM L22 Device Identification Values DSU DID.DEVSEL Device L22N18 L22N17 L22N16 0x3-0x4 Reserved L22J18 L22J17 L22J16 0x8-0x9 Reserved L22G18 L22G17 L22G16 0xD-0xFF Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 18 (DSU.DID.REVISION): The device variant denotes functional differences, whereas the die revision marks evolution of the die. Related Links DSU - Device Service Unit on page 76 on page 100 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 19: Block Diagram

    CONTROLLER COM[7:0] EVENT RESET RESETN XY[23..0] CONTROLLER PERIPHERAL TOUCH TAMPER[4:0] REAL TIME X[31..24] CONTROLLER COUNTER EVENT EVENT IN[11..0] FREQUENCY 4 x CCL OUT[3..0] METER EVENT Note:  Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 20 Some device configurations have different number of SERCOM instances, Timer/Counter instances, PTC signals and ADC signals. The number of PTC X and Y signals is configurable. Related Links Peripherals Configuration Summary on page 73 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 21: Pinout

    SAM L22G Figure 5-1. 48-Pin QFN, TQFP VDDIO PA25 PA24 PA23 SAM L22 VDDANA PA22 48-pins PA21 PA20 PA19 PA18 PA17 PA16 Figure 5-2. 49-Pin WLCSP (BOTTOM VIEW) Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 22: Sam L22J

    5.2. SAM L22J VDDIO PA25 PA24 PA23 PA22 GNDANA PA21 SAM L22 PA20 64-pins PB17 PB16 PA19 PA18 PA17 PA16 VDDIO Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 23: Sam L22N

    PA22 PA21 PA20 PB21 PB20 PB19 PB18 PB17 SAM L22 VDDANA PB16 VDDIO 100-pins PC21 PC20 PC19 PC18 PC17 PC16 PA19 PA18 PA17 PA16 VDDIO VDDANA Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 24: Signal Descriptions List

    Reset input Digital Serial Communication Interface - SERCOMx PAD[3:0] SERCOM Inputs/Outputs Pads Digital Oscillators Control - OSCCTRL Crystal or external clock Input Analog/Digital XOUT Crystal Output Analog Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 25 Digital Segment LCD SLCD51 - SLCD00 Segment LCD Analog VLCD Bias Voltage Analog Universal Serial Bus - USB DP for USB Digital DM for USB Digital Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 26 Type Active Level SOF 1kHz USB Start of Frame Digital Real Timer Clock - RTC RTC_IN[4:0] Tamper or external wake-up pins Digital RTC_OUT Tamper output Digital Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 27: I/O Multiplexing And Considerations

    SLCD/ SERCOM0/ SERCOM4/ TCC/ GCLK/ CCL/IN[5] XY[1] LP[13] PAD[2] PAD[2] WO[2] IO[4] PA11 EIC/EXTINT[11] PTC/ SLCD/ SERCOM0/ SERCOM4/ TCC/ CCL/ XY[0] LP[14] PAD[3] PAD[3] WO[3] OUT[1] Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 28 EIC/EXTINT[13] SERCOM2/ SERCOM5/ TC/1/ TCC/ USB/DP CCL/ PAD[3] PAD[1] WO[1] WO[1] OUT[2] PB22 EIC/EXTINT[6] SERCOM0/ SERCOM5/ TC/3/ TCC/ USB/SOF_1KHZ GCLK/ CCL/IN[0] PAD[2] PAD[2] WO[0] WO[2] IO[0] Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 29: Other Functions

    The oscillators are not mapped to the normal PORT functions and their multiplexing is controlled by registers in the Oscillators Controller (OSCCTRL) and in the 32K Oscillators Controller (OSC32KCTRL). Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 30 SERCOM instance. Table 7-5. SERCOM USART and I C Protocols SERCOM Instance Protocol SERCOM0 SERCOM1 SERCOM2 SERCOM3 SERCOM4 SERCOM5 C at 3.4MHz Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 31 V DDIO pin E1, V DDIO pin A5 GND pin D4, GND pin B3 PA00, PA01, PA30, PA31, PB02, PB03 V DDIO pin A5 GND pin B3 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 32: Power Supply And Start-Up Considerations

    PA[1:0] OSCULP32K XOSC32K CPU, Peripherals DFLL48M FDPLL96M The Atmel SAM L22 power domains are not independent of each other: • VDDCORE and VDDIO share GND, whereas VDDANA refers to GNDANA. • VDDCORE serves as the internal voltage regulator output. •...
  • Page 33 The following figure shows the recommended power supply connection. Figure 8-1. Power Supply Connection for Linear Mode Only SAM L22 VBAT (PB03) VDDANA Main Supply (1.62V — 3.63V) VDDIO VDDOUT VDDCORE GNDANA Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 34 One integrated power-on reset (POR) circuits monitoring VDDIO requires a minimum rise rate. 8.2.4.3. Maximum Rise Rate The rise rate of the power supplies must not exceed the values described in Electrical Characteristics. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 35: Power-Up

    Power-On Reset and Brown-Out Detector The SAM L22 embeds three features to monitor, warn and/or reset the device: • POR: Power-on Reset on VSWOUT and VDDIO Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 36: Performance Level Overview

    SERCOM: the maximum frequency is by factor 4 compared to PL2 List of peripherals/clock sources with full capabilities in PL0: • • • • OSC16M • Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 37 Full functionality and capability will be ensured in PL2. When transitioning between performance levels, the Supply Controller (SUPC) will provide a configurable smooth voltage scaling transition. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 38: Product Mapping

    0xFFFFFFFF AHB-APB Bridge B 0x42002C00 0x41000000 0x42003000 0x41002000 0x42003800 0x40004000 NVMCTRL 0x42003C00 SLCD 0x40006000 0x42004000 PORT 0x40008000 DMAC 0x42004400 TRNG 0x4000A000 0x42004800 0x4000C000 HMATRIXHS 0x42004C00 Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 39: Memories

    Note:  1. x = G, J, or E. Table 10-3. RWW Section Parameters Device Flash size [KB] Number of pages Page size [Bytes] SAML22x18 SAML22x17 SAML22x16 Note:  1. x = G, J, or E. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 40: Nvm User Row Mapping

    — 63:48 LOCK NVM Region Lock Bits. 0xFFFF NVMCTRL Related Links NVMCTRL – Non-Volatile Memory Controller on page 515 SUPC – Supply Controller on page 279 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 41: Nvm Software Calibration Area Mapping

    Word 0: 0x0080A00C Word 1: 0x0080A040 Word 2: 0x0080A044 Word 3: 0x0080A048 The uniqueness of the serial number is guaranteed only when using all 128 bits. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 42: Processor And Architecture

    Software can set the priority of each interrupt. The NVIC and the Cortex-M0+ processor core are closely coupled, providing low latency interrupt processing and efficient processing of late Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 43 I/Os. This enables single cycle I/O access to be sustained for as long as necessary. Related Links CPU Local Bus on page 541 PORT: IO Pin Controller on page 538 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 44: Nested Vector Interrupt Controller

    RTC – Real Time Counter EIC – External Interrupt Controller FREQM - Frequency Meter USB - Universal Serial Bus NVMCTRL – Non-Volatile Memory Controller DMAC - Direct Memory Access Controller Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 45: Micro Trace Buffer

    An execution trace packet consists of a pair of 32-bit words that the MTB generates when it detects a non-sequential change of the program pounter (PC) value. A non-sequential PC change can occur during Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 46: High-Speed Bus System

    Symmetric crossbar bus switch implementation • Allows concurrent accesses from different masters to different slaves • 32-bit data bus • Operation at a one-to-one clock frequency with the bus masters Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 47 High-Speed Bus Matrix Slaves Slave ID Internal Flash Memory SRAM Port 0 - CM0+ Access SRAM Port 1 - DSU Access AHB-APB Bridge B AHB-APB Bridge A Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 48 Bus Matrix 0x4100C114, M0+ Processor bits[1:0] DSU - Device Bus Matrix 0x4100201C, Service Unit bits[1:0] DMAC - Direct Bus Matrix Memory Access QOSCTRL.DQOS Controller - Data Access Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 49 QOSCTRL.WRBQ Controller - Write- Back Access USB - Universal Direct IP-QOSCTRL Serial Bus MTB - Micro Trace Direct STATIC-3 Buffer Note:  1. Using 32-bit access only. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 50: Pac - Peripheral Access Controller

    The events can trigger other operations in the system without exiting sleep modes. Related Links Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 51: Functional Description

    The Peripheral Access Control module allows the user to set a write protection on peripheral modules and generate an interrupt in case of a peripheral access violation. The peripheral’s protection can be set, Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 52 The “clear protection” operation will remove the write access protection for the peripheral selected by WRCTRL.PERID. Write accesses are allowed for the registers in this peripheral. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 53 The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the PAC is reset. All interrupt requests from the peripheral are ORed together Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 54 In Sleep mode, the PAC is kept enabled if an available master (CPU, DMA) is running. The PAC will continue to catch access errors from module and generate interrupts or events. 12.5.7. Synchronization Not applicable. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 55: Register Summary

    OSC32KCTR 0x34 GCLK SUPC OSCCTRL RSTC MCLK 0x35 STATUSA 15:8 FREQM 0x36 23:16 0x37 31:24 0x38 DMAC PORT NVMCTRL 0x39 15:8 STATUSB 0x3A 23:16 0x3B 31:24 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 56: Register Description

    "PAC Write-Protection" property in each individual register description. For details, refer to the related links. Related Links Register Synchronization on page 116 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 57 Where BridgeNumber represents the Peripheral Bridge Number (0 for Peripheral Bridge A, 1 for Peripheral Bridge B, etc). N represents the peripheral index from the respective Bridge Number: Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 58 Table 12-2. PERID Values Periph. Bridge Name BridgeNumber PERID Values 32+N 64+N 96+N 128+N Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 59 (INTFLAGAHB, INTFLAGn) is set: Value Description Peripheral Access Error Event Output is disabled. Peripheral Access Error Event Output is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 60 Writing a one to this bit will clear the Peripheral Access Error interrupt Enable bit and disables the corresponding interrupt request. Value Description Peripheral Access Error interrupt is disabled. Peripheral Access Error interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 61 Writing a one to this bit will set the Peripheral Access Error interrupt Enable bit and enables the corresponding interrupt request. Value Description Peripheral Access Error interrupt is disabled. Peripheral Access Error interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 62 Bit 3 – HPB1: Interrupt Flag for SLAVE HPB1 Bit 2 – HSRAMDSU: Interrupt Flag for SLAVE HSRAMDSU Bit 1 – HSRAMCM0P: Interrupt Flag for SLAVE HSRAMCM0P Bit 0 – FLASH: Interrupt Flag for SLAVE FLASH Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 63 Bit 6 – SUPC: Interrupt Flag for SUPC Bit 5 – OSC32KCTRL: Interrupt Flag for OSC32KCTRL Bit 4 – OSCCTRL: Interrupt Flag for OSCCTRL Bit 3 – RSTC: Interrupt Flag for RSTC Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 64 Bit 2 – MCLK: Interrupt Flag for MCLK Bit 1 – PM: Interrupt Flag for PM Bit 0 – PAC: Interrupt Flag for PAC Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 65 Bit 3 – PORT: Interrupt Flag for PORT Bit 2 – NVMCTRL: Interrupt Flag for NVMCTRL Bit 1 – DSU: Interrupt Flag for DSU Bit 0 – USB: Interrupt Flag for USB Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 66 Bit 13 – AC: Interrupt Flag for AC Bit 12 – ADC: Interrupt Flag for ADC Bit 7 – TCC: Interrupt Flag for TCC Bit 0 – EVSYS: Interrupt Flag for EVSYS Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 67 Bits 8, 9, 10, 11 – TCn: Interrupt Flag for TCn [n = 3..0] Bits 1, 2, 3, 4, 5, 6 – SERCOMn: Interrupt Flag for SERCOMn [n = 5..0] Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 68 Bit 7 – GCLK: Peripheral GCLK Write Protection Status Bit 6 – SUPC: Peripheral SUPC Write Protection Status Bit 5 – OSC32KCTRL: Peripheral OSC32KCTRL Write Protection Status Bit 4 – OSCCTRL: Peripheral OSCCTRL Write Protection Status Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 69 Bit 3 – RSTC: Peripheral RSTC Write Protection Status Bit 2 – MCLK: Peripheral MCLK Write Protection Status Bit 1 – PM: Peripheral PM Write Protection Status Bit 0 – PAC: Peripheral PAC Write Protection Status Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 70 Bit 3 – PORT: Peripheral PORt Write Protection Status Bit 2 – NVMCTRL: Peripheral NVMCTRL Write Protection Status Bit 1 – DSU: Peripheral DSU Write Protection Status Bit 0 – USB: Peripheral USB Write Protection Status Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 71 Bit 14 – PTC: Peripheral PTC Write Protection Status Bit 13 – AC: Peripheral ADC Write Protection Status Bit 12 – ADC: Peripheral ADC Write Protection Status Bit 7 – TCC: Peripheral TCC Write Protection Status Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 72 Bits 8, 9, 10, 11 – TCn: Peripheral TCn Write Protection Status [n = 3..0] Bits 1, 2, 3, 4, 5, 6 – SERCOMn: Peripheral SERCOMn Write Protection Status [n = 5..0] Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 73: Peripherals Configuration Summary

    — — — — PDTOP Bridge B 0x41000 — — — PDTOP 0x41002 — — — — — PDTOP NVMCT 0x41004 — — — — PDTOP Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 74 — 17: EVU 47: OVF 25: OVF PDTOP 48-49: 26-27: MC0-1 MC0-1 0x42002 — — 18: EVU 50: OVF 28: OVF PDTOP 51-52: 29-30: MC0-1 MC0-1 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 75 64 : — PDTOP READY 0x42004 — — — 24 : 65 : — PDTOP LUTIN0 LUTOUT 25 : LUTIN1 66 : LUTOUT LUTIN2 LUTOUT LUTIN3 LUTOUT Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 76: Dsu - Device Service Unit

    32-bit cyclic redundancy check (CRC32) of any memory accessible through the bus matrix ® ™ • CoreSight compliant device identification • Two debug communications channels • Debug access port security filter • Onboard memory built-in self-test (MBIST) Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 77: Block Diagram

    The DSU will continue to operate in any sleep mode where the selected source clock is running. Related Links PM – Power Manager on page 188 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 78: Debug Operation

    SWCLK is left unconnected. When the CPU is held in the reset extension phase, the CPU Reset Extension bit of the Status A register (STATUSA.CRSTEXT) is Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 79 The presence of a debugger probe is detected when either Hot-Plugging or Cold-Plugging is detected. Once detected, the Debugger Present bit of the Status B register (STATUSB.DBGPRES) is set. For Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 80: Chip Erase

    POR threshold. The system continues to be held in this static state until the internally regulated supplies have reached a safe operating state. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 81: Intellectual Property Protection

    CPU. If the device is protected and an access is issued in the region 0x100-0x1FF, it is subject to security restrictions. For more information, refer to the Table 14-1. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 82: 14.10. Device Identification

    523 14.10. Device Identification Device identification relies on the ARM CoreSight component identification scheme, which allows the chip to be identified as an Atmel device implementing a DSU. The DSU contains identification registers to differentiate the device. 14.10.1. CoreSight Identification A system-level ARM CoreSight ROM table is present in the device to identify the vendor and the chip identification method.

  • Page 83: 14.11. Functional Description

    Hence, the user must wait for the STATUSA.DONE bit to be set prior to issuing another one. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 84 The initial value used for the CRC32 calculation must be written to the Data register (DATA). This value will usually be 0xFFFFFFFF, but can be, for example, the result of a previous CRC32 calculation if generating a common CRC32 of separate memory blocks. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 85 The algorithm used for testing is a type of March algorithm called "March LR". This algorithm is able to detect a wide range of memory defects, while still keeping a linear run time. The algorithm is: Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 86 DATA: contains data to identify which bit failed, and during which phase of the test it failed. The DATA register will in this case contains the following bit groups: Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 87 14.11.6. System Services Availability when Accessed Externally External access: Access performed in the DSU address offset 0x200-0x1FFF range. Internal access: Access performed in the DSU address offset 0x0-0x100 range. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 88 Yes, only full array or full EEPROM CoreSight Compliant Device identification Debug communication channels Testing of onboard memories (MBIST) STATUSA.CRSTEXT clearing No (STATUSA.PERR is set when attempting to do Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 89: 14.12. Register Summary

    0x1003 31:24 ADDOFF[19:12] 0x1004 EPRES 0x1005 15:8 ADDOFF[3:0] ENTRY1 0x1006 23:16 ADDOFF[11:4] 0x1007 31:24 ADDOFF[19:12] 0x1008 END[7:0] 0x1009 15:8 END[15:8] 0x100A 23:16 END[23:16] 0x100B 31:24 END[31:24] Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 90 PREAMBLE[3:0] 0x1FF5 15:8 CID1 0x1FF6 23:16 0x1FF7 31:24 0x1FF8 PREAMBLEB2[7:0] 0x1FF9 15:8 CID2 0x1FFA 23:16 0x1FFB 31:24 0x1FFC PREAMBLEB3[7:0] 0x1FFD 15:8 CID3 0x1FFE 23:16 0x1FFF 31:24 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 91: 14.13. Register Description

    Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to Register Access Protection. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 92 Writing a '1' to this bit starts the cyclic redundancy check algorithm. Bit 0 – SWRST: Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets the module. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 93 Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Done bit. This bit is set when a DSU operation is completed. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 94 Writing a '0' to this bit has no effect. Writing a '1' to this bit has no effect. This bit is set when DCCx is written. This bit is cleared when DCCx is read. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 95 Bit description when operating CRC32: refer to 32-bit Cyclic Redundancy Check CRC32 Bit description when testing onboard memories (MBIST): refer to Testing of On-Board Memories MBIST Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 96 PAC Write-Protection   LENGTH[29:22] Access Reset LENGTH[21:14] Access Reset LENGTH[13:6] Access Reset LENGTH[5:0] Access Reset Bits 31:2 – LENGTH[29:0]: Length Length in words needed for memory operations. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 97 PAC Write-Protection   DATA[31:24] Access Reset DATA[23:16] Access Reset DATA[15:8] Access Reset DATA[7:0] Access Reset Bits 31:0 – DATA[31:0]: Data Memory operation initial value or result value. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 98 Name:  DCC0 Offset:  0x0010 Reset:  0x00000000 Property:   DATA[31:24] Access Reset DATA[23:16] Access Reset DATA[15:8] Access Reset DATA[7:0] Access Reset Bits 31:0 – DATA[31:0]: Data Data register. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 99 Name:  DCC1 Offset:  0x0014 Reset:  0x00000000 Property:   DATA[31:24] Access Reset DATA[23:16] Access Reset DATA[15:8] Access Reset DATA[7:0] Access Reset Bits 31:0 – DATA[31:0]: Data Data register. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 100 Note:  The device variant (last letter of the ordering number) is independent of the die revision (DSU.DID.REVISION): The device variant denotes functional differences, whereas the die revision marks evolution of the die. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 101 This bit field identifies a device within a product family and product series. Refer to the Ordering Information for device configurations and corresponding values for Flash memory density, pin count and device variant. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 102 This bit is set at power-up if the device is not protected indicating that the entry is not present. This bit is cleared at power-up if the device is not protected indicating that the entry is present. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 103 This bit is set at power-up if the device is not protected indicating that the entry is not present. This bit is cleared at power-up if the device is not protected indicating that the entry is present. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 104 END[31:24] Access Reset END[23:16] Access Reset END[15:8] Access Reset END[7:0] Access Reset Bits 31:0 – END[31:0]: End Marker Indicates the end of the CoreSight ROM table entries. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 105 This bit is cleared at power-up if the device is protected, indicating that the system memory is not accessible from a debug adapter. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 106 These bits will always return zero when read, indicating that this debug component occupies one 4KB block. Bits 3:0 – JEPCC[3:0]: JEP-106 Continuation Code These bits will always return zero when read, indicating an Atmel device. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 107 PARTNBL[7:0] Access Reset Bits 7:0 – PARTNBL[7:0]: Part Number Low These bits will always return 0xD0 when read, indicating that this device implements a DSU module instance. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 108 Access Reset Bits 7:4 – JEPIDCL[3:0]: Low part of the JEP-106 Identity Code These bits will always return 0xF when read, indicating a Atmel device (Atmel JEP-106 identity code is 0x1F). Bits 3:0 – PARTNBH[3:0]: Part Number High These bits will always return 0xC when read, indicating that this device implements a DSU module instance.
  • Page 109 This bit will always return one when read, indicating that JEP-106 code is used. Bits 2:0 – JEPIDCH[2:0]: JEP-106 Identity Code High These bits will always return 0x1 when read, indicating an Atmel device (Atmel JEP-106 identity code is 0x1F). Atmel SAM L22G / L22J / L22N [DATASHEET]...
  • Page 110 Bits 7:4 – REVAND[3:0]: Revision Number These bits will always return 0x0 when read. Bits 3:0 – CUSMOD[3:0]: ARM CUSMOD These bits will always return 0x0 when read. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 111 0x0000000D Property:   Access Reset Access Reset Access Reset PREAMBLEB0[7:0] Access Reset Bits 7:0 – PREAMBLEB0[7:0]: Preamble Byte 0 These bits will always return 0xD when read. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 112 These bits will always return 0x1 when read indicating that this ARM CoreSight component is ROM table (refer to the ARM Debug Interface v5 Architecture Specification at http://www.arm.com). Bits 3:0 – PREAMBLE[3:0]: Preamble These bits will always return 0x0 when read. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 113 0x00000005 Property:   Access Reset Access Reset Access Reset PREAMBLEB2[7:0] Access Reset Bits 7:0 – PREAMBLEB2[7:0]: Preamble Byte 2 These bits will always return 0x05 when read. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 114 0x000000B1 Property:   Access Reset Access Reset Access Reset PREAMBLEB3[7:0] Access Reset Bits 7:0 – PREAMBLEB3[7:0]: Preamble Byte 3 These bits will always return 0xB1 when read. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 115: Clock System

    Generic Clocks: These are clock signals generated by Generic Clock Generators and output by the Peripheral Channels, and serve as clocks for the peripherals of the system. Multiple Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 116: Synchronous And Asynchronous Clocks

    All peripherals are composed of one digital bus interface connected to the APB or AHB bus and running from a corresponding clock in the Main Clock domain, and one peripheral core running from the peripheral Generic Clock (GCLK). Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 117 When write-synchronization is ongoing for a register, any subsequent write attempts to this register will be discarded, and an error will be reported. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 118 SYNCBUSY.SWRST. When writing a ‘1’ to the CTRLA.SWRST bit it will immediately read as ‘1’. CTRL.SWRST and SYNCBUSY.SWRST will be cleared by hardware when the peripheral has been reset. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 119: Enabling A Peripheral

    = Clock source startup time + 1 × clock source period + 1 × divided clock source period start_min The time between the last active clock request stopped and the clock is shut down, T , is between: stop Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 120: Power Consumption Vs. Speed

    • Generic Clocks that are write-locked, i.e., the according WRTLOCK is set to 1 prior to Reset Related Links RSTC – Reset Controller on page 181 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 121: Gclk - Generic Clock Controller

    DPLL96M Peripheral Channel OSC16M GCLK_PERIPH DFLL48M OSC32CTRL Clock Clock PERIPHERAL Divider & Gate XOSC32K Masker OSCULP32K GCLK_IO GCLK_MAIN MCLK The GCLK block diagram is shown below: Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 122: Signal Description

    In order to use this peripheral, other parts of the system must be configured correctly, as described below. 16.5.1. I/O Lines Using the GCLK I/O lines requires the I/O pins to be configured. Related Links PORT - I/O Pin Controller on page 538 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 123: Functional Description

    A clock source selected as input to a Generator can either be used directly, or it can be prescaled in the Generator. A generator output is used by one or more Peripheral Channels to provide a peripheral generic clock signal (GCLK_PERIPH) to the peripherals. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 124 Controller. Refer to the Main Clock Controller description for details on the synchronous clock generation. Figure 16-3. Generic Clock Generator Related Links MCLK – Main Clock on page 141 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 125 Run In Standby bit of the Generic Control register (GENCTRLn.RUNSTDBY) is zero. If GENCTRLn.RUNSTDBY is '1', the GCLKGEN clock is kept running and output to the I/O pin. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 126 The Generator source of a locked Peripheral Channel will be locked, too: The corresponding GENCTRLn register is locked, and can be unlocked only by a Power Reset. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 127 The following table identifies when a Clock Generator is off in Standby Mode, minimizing the power consumption: Table 16-2. Clock Generator n Activity in Standby Mode Request for Clock n GENCTRLn.RUNSTDB GENCTRLn.OE Clock Generator n present active active Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 128 Control A register (CTRLA) Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Related Links CTRLA on page 133 PCHCTRLmn on page 138 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 129: Register Summary

    DIV[15:8] 0x34 Reserved 0x7F 0x80 WRTLOCK CHEN GEN[3:0] 0x81 15:8 PCHCTRLm0 0x82 23:16 0x83 31:24 0x84 WRTLOCK CHEN GEN[3:0] 0x85 15:8 PCHCTRLm1 0x86 23:16 0x87 31:24 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 130 0xAA 23:16 0xAB 31:24 0xAC WRTLOCK CHEN GEN[3:0] 0xAD 15:8 PCHCTRLm11 0xAE 23:16 0xAF 31:24 0xB0 WRTLOCK CHEN GEN[3:0] 0xB1 15:8 PCHCTRLm12 0xB2 23:16 0xB3 31:24 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 131 0xD6 23:16 0xD7 31:24 0xD8 WRTLOCK CHEN GEN[3:0] 0xD9 15:8 PCHCTRLm22 0xDA 23:16 0xDB 31:24 0xDC WRTLOCK CHEN GEN[3:0] 0xDD 15:8 PCHCTRLm23 0xDE 23:16 0xDF 31:24 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 132: Register Description

    Some registers are synchronized when read and/or written. Synchronization is denoted by the "Write- Synchronized" or the "Read-Synchronized" property in each individual register description. For details, refer to Synchronization. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 133 Reset. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. Value Description There is no Reset operation ongoing. A Reset operation is ongoing. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 134 This bit is set when the synchronization of the Generator Control n register (GENCTRLn) between clock domains is started. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 135 This bit is used to keep the Generator running in Standby as long as it is configured to output to a dedicated GCLK_IO pin. If GENCTRLn.OE is zero, this bit has no effect and the generator will only be running if a peripheral requires the clock. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 136 Generator output clock duty cycle is not balanced to 50/50 for odd division factors. Generator output clock duty cycle is 50/50. Bit 8 – GENEN: Generator Enable This bit is used to enable and disable the Generator. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 137 GCLK Generator Reset Value after a User Reset 0x00000105 others No change if the generator is used by a Peripheral Channel m with PCHCTRLm.WRTLOCK=1 else 0x00000000 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 138 Bits 3:0 – GEN[3:0]: Generator Selection This bit field selects the Generator to be used as the source of a peripheral clock, as shown in the table below: Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 139 FDPLL96M 32kHz clock for FDPLL96M internal lock timer GCLK_EIC GCLK_FREQM_MSR FREQM Measure GCLK_FREQM_REF FREQM Reference GCLK_EVSYS_CHANNEL_0 EVSYS_CHANNEL_0 GCLK_EVSYS_CHANNEL_1 EVSYS_CHANNEL_1 GCLK_EVSYS_CHANNEL_2 EVSYS_CHANNEL_2 GCLK_EVSYS_CHANNEL_3 EVSYS_CHANNEL_3 GCLK_EVSYS_CHANNEL_4 EVSYS_CHANNEL_4 GCLK_EVSYS_CHANNEL_5 EVSYS_CHANNEL_5 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 140 GCLK_EVSYS_CHANNEL_7 EVSYS_CHANNEL_7 GCLK_SERCOM[0,1,2,3,4,5]_SLOW SERCOM[0,1,2,3,4,5]_SLOW GCLK_SERCOM0_CORE SERCOM0_CORE GCLK_SERCOM1_CORE SERCOM1_CORE GCLK_SERCOM2_CORE SERCOM2_CORE GCLK_SERCOM3_CORE SERCOM3_CORE GCLK_SERCOM4_CORE SERCOM4_CORE GCLK_SERCOM5_CORE SERCOM5_CORE GCLK_TCC0 TCC0 GCLK_TC0, GCLK_TC1 TC0, TC1 GCLK_TC2, GCLK_TC3 TC2, TC3 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 141: Mclk - Main Clock

    17.5. Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 17.5.1. I/O Lines Not applicable. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 142 The interrupt request line is connected to the Interrupt Controller. Using the MCLK interrupt requires the Interrupt Controller to be configured first. 17.5.6. Events Not applicable. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 143: Functional Description

    Refer to the Generic Clock Controller description for details on how to configure the clock source of the GCLK_MAIN clock. Related Links GCLK - Generic Clock Controller on page 121 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 144 Electrical Characteristics on page 1147 17.6.2.5. Clock Ready Flag There is a slight delay between writing to CPUDIV and BUPDIV until the new clock settings become effective. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 145 CLK_EIC_APB Enabled CLK_EVSYS_APB Enabled CLK_FREQM_APB Enabled CLK_GCLK_APB Enabled CLK_MCLK_APB Enabled CLK_NVMCTRL_AHB Enabled CLK_NVMCTRL_APB Enabled CLK_OSCCTRL_APB Enabled CLK_PAC_AHB Enabled CLK_PAC_APB Enabled CLK_PORT_APB Enabled CLK_PTC_APB Enabled CLK_SERCOM0_APB Enabled Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 146 APBx bridge, will make it impossible to write the mask registers again. In this case, they can only be re-enabled by a system reset. 17.6.3. DMA Operation Not applicable. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 147 In IDLE sleep mode, the MCLK is still running on the selected main clock. In STANDBY sleep mode, the MCLK is frozen if no synchronous clock is required. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 148: Register Summary

    Some registers can be write-protected optionally by the Peripheral Access Controller (PAC). This is denoted by the property "PAC Write-Protection" in each individual register description. Refer to the Register Access Protection for details. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 149 17.8.1. Control A All bits in this register are reserved. Name:  CTRLA Offset:  0x00 Reset:  0x00 Property: PAC Write-Protection   Access Reset Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 150 The Clock Ready interrupt is disabled. The Clock Ready interrupt is enabled and will generate an interrupt request when the Clock Ready Interrupt Flag is set. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 151 Writing a '1' to this bit will set the Clock Ready Interrupt Enable bit and enable the Clock Ready interrupt. Value Description The Clock Ready interrupt is disabled. The Clock Ready interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 152 CLKCFG registers and will generate an interrupt if INTENCLR/SET.CKRDY is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Clock Ready interrupt flag. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 153 DIV8 Divide by 8 0x10 DIV16 Divide by 16 0x20 DIV32 Divide by 32 0x40 DIV64 Divide by 64 0x80 DIV128 Divide by 128 others Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 154 DIV8 Divide by 8 0x10 DIV16 Divide by 16 0x20 DIV32 Divide by 32 0x40 DIV64 Divide by 64 0x80 DIV128 Divide by 128 others Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 155 Bit 5 – DSU: DSU AHB Clock Enable Value Description The AHB clock for the DSU is stopped. The AHB clock for the DSU is enabled. Bit 4 – USB: USB AHB Clock Enable Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 156 Reserved bits are unused and reserved for future use. For compatibility with future devices, always write reserved bits to their reset value. If no reset value is given, write 0. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 157 The APBA clock for the EIC is enabled. Bit 9 – RTC: RTC APBA Clock Enable Value Description The APBA clock for the RTC is stopped. The APBA clock for the RTC is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 158 Bit 2 – MCLK: MCLK APBA Clock Enable Value Description The APBA clock for the MCLK is stopped. The APBA clock for the MCLK is enabled. Bit 1 – PM: PM APBA Clock Enable Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 159 The APBA clock for the PM is enabled. Bit 0 – PAC: PAC APBA Clock Enable Value Description The APBA clock for the PAC is stopped. The APBA clock for the PAC is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 160 Bit 1 – DSU: DSU APBB Clock Enable Value Description The APBB clock for the DSU is stopped The APBB clock for the DSU is enabled Bit 0 – USB: USB APBB Clock Enable Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 161 Reserved bits are unused and reserved for future use. For compatibility with future devices, always write reserved bits to their reset value. If no reset value is given, write 0. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 162 Bit 16 – AES: AES APBC Mask Clock Enable Value Description The APBC clock for the AES is stopped. The APBC clock for the AES is enabled. Bit 15 – SLCD: SLCD APBC Clock Enable Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 163 Bit 8 – TC0: TC0 APBC Mask Clock Enable Value Description The APBC clock for the TC0 is stopped. The APBC clock for the TC0 is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 164 Bit 1 – SERCOM0: SERCOM0 APBC Mask Clock Enable Value Description The APBC clock for the SERCOM0 is stopped. The APBC clock for the SERCOM0 is enabled. Bit 0 – EVSYS: EVSYS APBC Clock Enable Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 165 Value Description The APBC clock for the EVSYS is stopped. The APBC clock for the EVSYS is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 166: Freqm - Frequency Meter

    18.4. Signal Description Not applicable. 18.5. Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 167 Protection" property in each individual register description. Write-protection does not apply to accesses through an external debugger. Related Links PAC - Peripheral Access Controller on page 50 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 168: Functional Description

    Interrupt Flag Status and Clear register (INTFLAG.DONE) will be set and an interrupt request is generated. The result of the measurement can be read from the Value register (VALUE.VALUE). The frequency of the measured clock GCLK_FREQM_MSR is then: Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 169 Software Reset bit in Control A register (CTRLA.SWRST) • Enable bit in Control A register (CTRLA.ENABLE) Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 170 Related Links Register Synchronization on page 116 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 171: Register Summary

    Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-protection is denoted by the "PAC Write-Protection" property in each individual register description. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 172 CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. This bit is not enable-protected. Value Description There is no reset operation ongoing. The reset operation is ongoing. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 173 0x00 Property: –   START Access Reset Bit 0 – START: Start Measurement Value Description Writing a '0' has no effect. Writing a '1' starts a measurement. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 174 Bits 7:0 – REFNUM[7:0]: Number of Reference Clock Cycles Selects the duration of a measurement in number of CLK_FREQM_REF cycles. This must be a non-zero value, i.e. 0x01 (one cycle) to 0xFF (255 cycles). Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 175 Writing a '1' to this bit will clear the Measurement Done Interrupt Enable bit, which disables the Measurement Done interrupt. Value Description The Measurement Done interrupt is disabled. The Measurement Done interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 176 Writing a '1' to this bit will set the Measurement Done Interrupt Enable bit, which enables the Measurement Done interrupt. Value Description The Measurement Done interrupt is disabled. The Measurement Done interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 177 This flag is set when the STATUS.BUSY bit has a one-to-zero transition. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the DONE interrupt flag. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 178 Writing a '1' to this bit will clear the OVF status. Bit 0 – BUSY: FREQM Status Value Description No frequency measurement ongoing. Frequency measurement is ongoing. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 179 Bit 0 – SWRST: Synchronization Busy This bit is cleared when the synchronization of CTRLA.SWRST is complete. This bit is set when the synchronization of CTRLA.SWRST is started. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 180 Offset:  0x10 Reset:  0x00000000 Property: –   Access Reset VALUE[23:16] Access Reset VALUE[15:8] Access Reset VALUE[7:0] Access Reset Bits 23:0 – VALUE[23:0]: Measurement Value Result from measurement. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 181: Rstc - Reset Controller

    RCAUSE BKUPEXIT BBPS SUPC 19.4. Signal Description Signal Name Type Description RESET Digital input External reset One signal can be mapped on several pins. Related Links Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 182: Product Dependencies

    19.5.9. Analog Connections Not applicable. 19.6. Functional Description 19.6.1. Principle of Operation The Reset Controller collects the various Reset sources and generates Reset for the device. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 183 Real-Time Counter interrupt. For details refer to the applicable INTFLAG in the RTC for details. If one of these conditions is triggered in Backup Mode, the RCAUSE.BACKUP bit is set and the Backup Exit Register (BKUPEXIT) is updated. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 184 19.6.4. DMA Operation Not applicable. 19.6.5. Interrupts Not applicable. 19.6.6. Events Not applicable. 19.6.7. Sleep Mode Operation The RSTC module is active in all sleep modes. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 185: Register Summary

    Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to Register Access Protection. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 186 Bit 1 – BOD12: Brown Out 12 Detector Reset This bit is set if a BOD12 Reset has occurred. Bit 0 – POR: Power On Reset This bit is set if a POR has occurred. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 187 Bit 1 – RTC: Real Timer Counter Interrupt This bit is set if an RTC interrupt flag is set in Backup Mode. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 188: Pm - Power Manager

    POWER LEVEL SWITCHES POWER DOMAIN FOR POWER DOMAINS CONTROLLER STDBYCFG SLEEP MODE SUPPLY MAIN CLOCK CONTROLLER CONTROLLER CONTROLLER SLEEPCFG PERFORMANCE LEVEL CONTROLLER PLCF 20.4. Signal Description Not applicable. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 189: Product Dependencies

    Write-protection does not apply to accesses through an external debugger. Related Links PAC - Peripheral Access Controller on page 50 20.5.8. Analog Connections Not applicable. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 190: Functional Description

    Backup sleep mode: Only the backup domain is kept powered to allow few features to run (RTC, 32KHz clock sources, and wake-up from external pins). • Off sleep mode: The entire device is powered off. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 191 The sleep modes (idle, standby, backup, and off) and their effect on the clocks activity, the regulator and the NVM state are described in the table and the sections below. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 192 For example, a peripheral running on a GCLK clock can trigger an interrupt. When the enabled asynchronous wake-up event occurs and the system is woken up, the device will either Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 193 The Performance Level Disable bit in the Performance Level Configuration register (PLCFG.PLDIS) can be used to freeze the performance level to PL0. This disables the performance level hardware Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 194 The RAM is in low-power mode if the device is in standby mode. Refer to RAM Automatic Low Power Mode for details. • Non-Volatile Memory - the NVM is automatically set in low power mode in these conditions: Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 195 Note:  In standby sleep mode, the RAM is put in low-power mode by default. This means that the RAM is back-biased, and the DMAC cannot access it. The DMAC can only access the RAM when it is not back biased (PM.STDBYCFG.BBIASxx=0x0). Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 196 (used in active mode), and the main voltage regulator used to execute the sleepwalking task is the selected regulator used in active mode (LDO or Buck converter). These are illustrated in the figure below. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 197 Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 198 Nested Vector Interrupt Controller on page 44 Interrupt Line Mapping on page 44 20.6.7. Events Not applicable. 20.6.8. Sleep Mode Operation The Power Manager is always active. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 199: Register Summary

    Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to Register Access Protection. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 200 After waking up from Backup mode, I/O lines are not held. After waking up from Backup mode, I/O lines are held until IORET is written to 0. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 201 Reserved STANDBY ALL clocks are OFF, unless requested by sleepwalking peripheral BACKUP Only Backup domain is powered ON All power domains are powered OFF Reserved Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 202 The Performance Level mechanism is enabled. The Performance Level mechanism is disabled. Bits 1:0 – PLSEL[1:0]: Performance Level Select Value Name Definition Performance Level 0 Reserved Reserved Performance Level 2 Reserved Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 203 The Performance Ready interrupt is disabled. The Performance Ready interrupt is enabled and will generate an interrupt request when the Performance Ready Interrupt Flag is set. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 204 Writing a '1' to this bit will set the Performance Ready Interrupt Enable bit and enable the Performance Ready interrupt. Value Description The Performance Ready interrupt is disabled. The Performance Ready interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 205 This flag is set when the performance level is ready and will generate an interrupt if INTENCLR/ SET.PLRDY is '1'. Writing a '1' to this bit has no effect. Writing a '1' to this bit clears the Performance Ready interrupt flag. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 206 Bits 7:6 – VREGSMOD[1:0]: VREG Switching Mode Refer to Regulator Automatic Low Power Mode for details. Value Name Description AUTO Automatic Mode PERFORMANCE Performance oriented Low Power consumption oriented Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 207: Oscctrl - Oscillators Controller

    32kHz to 2MHz reference clock – A selection of sources for the reference clock – Adjustable proportional integral controller – Fractional part used to achieve 1/16th of reference clock step Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 208: Block Diagram

    The DFLL48M control logic uses the DFLL oscillator output, which is also asynchronous to the user interface clock (CLK_OSCCTRL_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to Synchronization for further details. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 209: Functional Description

    21.6.2. External Multipurpose Crystal Oscillator (XOSC) Operation The XOSC can operate in two different modes: Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 210 STATUS.XOSCRDY if the External Multipurpose Crystal Oscillator Ready bit in the Interrupt Enable Set register (INTENSET.XOSCRDY) is set. Related Links GCLK - Generic Clock Controller on page 121 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 211 '1' to Switch Back Enable bit in the Clock Failure Control register (XOSCCTRL.SWBACK). Once the XOSC clock is switched back, the Switch Back bit (XOSCCTRL.SWBACK) is cleared by hardware. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 212 Active or Idle Always run Active or Idle Run if requested by peripheral Standby Always run Standby Run if requested by peripheral Standby Run if requested by peripheral Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 213 Select the multiplication factor in the DFLL Multiply Factor bit group (DFLLMUL.MUL) in the DFLL Multiplier register. Note:  When choosing DFLLMUL.MUL, the output frequency must not exceed the maximum frequency of the device. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 214 Enable the Bypass Coarse Lock (DFLLCTRL.BPLCKC=1). Start DFLL close loop (DFLLCTRL.MODE=1). Related Links NVM User Row Mapping on page 40 NVM Software Calibration Area Mapping on page 41 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 215 Control register (DFLLCTRL.QLDIS). The Quick Lock might lead to a larger spread in the output frequency than chill cycles, but the average output frequency is the same. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 216 When the controller is enabled, the relationship between the reference clock frequency and the output LDRFRAC clock frequency is: � = � × LDR + 1 + × PRESC Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 217 When the Lock Time bit field in the DPLL Control B register (DPLLCTRLB.LTIME) is non-zero, a user defined lock time is used to validate the lock operation. In this case the lock time is constant. If Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 218 When the prescaler field is modified, the DPLLSYNCBUSY.DPLLPRESC bit is set. It will be cleared by hardware when the synchronization is over. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 219 Not applicable. 21.6.8. Interrupts The OSCCTRL has the following interrupt sources: • XOSCRDY - Multipurpose Crystal Oscillator Ready: A 0-to-1 transition on the STATUS.XOSCRDY bit is detected Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 220 Writing a '0' to this bit disables the CFD output event. Refer to the Event System chapter for details on configuring the event system. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 221 The following bits need synchronization when written: • Enable bit in control register A (DPLLCTRLA.ENABLE) • DPLL Ratio register (DPLLRATIO) • DPLL Prescaler register (DPLLPRESC) Related Links Register Synchronization on page 116 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 222: Register Summary

    MUL[7:0] 0x21 15:8 MUL[15:8] DFLLMUL 0x22 23:16 FSTEP[7:0] 0x23 31:24 CSTEP[5:0] FSTEP[9:8] 0x24 DFLLSYNC READREQ 0x25 Reserved 0x27 0x28 DPLLCTRLA ONDEMAND RUNSTDBY ENABLE 0x29 Reserved 0x2B Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 223: Register Description

    Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-Synchronized" or "Write.Synchronized" property in each individual register description. Refer to the Synchronization section for details. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 224 Writing '0' to this bit has no effect. Writing '1' to this bit will set the DPLL Lock Timeout Interrupt Enable bit, which enables the DPLL Lock Timeout interrupt. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 225 The DFLL Lock Coarse interrupt is disabled. The DFLL Lock Coarse interrupt is enabled, and an interrupt request will be generated when the DFLL Lock Coarse Interrupt flag is set. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 226 Writing '0' to this bit has no effect. Writing '1' to this bit will set the XOSC Clock Failure Interrupt Enable bit, which enables the XOSC Clock Failure Interrupt. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 227 The XOSC Ready interrupt is disabled. The XOSC Ready interrupt is enabled, and an interrupt request will be generated when the XOSC Ready Interrupt flag is set. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 228 Writing '0' to this bit has no effect. Writing '1' to this bit will clear the DPLL Lock Timeout Interrupt Enable bit, which disables the DPLL Lock Timeout interrupt. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 229 The DFLL Lock Coarse interrupt is disabled. The DFLL Lock Coarse interrupt is enabled, and an interrupt request will be generated when the DFLL Lock Coarse Interrupt flag is set. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 230 Writing '0' to this bit has no effect. Writing '1' to this bit will clear the XOSC Clock Failure Interrupt Enable bit, which disables the XOSC Clock Failure interrupt. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 231 The XOSC Ready interrupt is disabled. The XOSC Ready interrupt is enabled, and an interrupt request will be generated when the XOSC Ready Interrupt flag is set. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 232 This flag is set on 0-to-1 transition of the DPLL Lock Fall bit in the Status register (STATUS.DPLLLCKF) and will generate an interrupt request if INTENSET.DPLLLCKF is '1'. Writing '0' to this bit has no effect. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 233 INTENSET.DFLLRDY is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the DFLL Ready interrupt flag. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 234 INTENSET.XOSCRDY is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the XOSC Ready interrupt flag. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 235 DPLL Lock time-out detected. Bit 17 – DPLLLCKF: DPLL Lock Fall Value Description DPLL Lock fall edge not detected. DPLL Lock fall edge detected. Bit 16 – DPLLLCKR: DPLL Lock Rise Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 236 Bit 4 – OSC16MRDY: OSC16M Ready Value Description OSC16M is not ready. OSC16M is stable and ready to be used as a clock source. Bit 2 – CLKSW: XOSC Clock Switch Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 237 A XOSC failure was detected. Bit 0 – XOSCRDY: XOSC Ready Value Description XOSC is not ready. XOSC is stable and ready to be used as a clock source. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 238 These bits select the prescaler for the clock failure detector. The OSC16M oscillator is used to clock the CFD prescaler. The CFD safe clock frequency is the OSC16M frequency divided by 2^CFDPRESC. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 239 Clock Failure detector event output is disabled and no event will be generated. Clock Failure detector event output is enabled and an event will be generated. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 240 Bits 3:2 – FSEL[1:0]: Oscillator Frequency Selection These bits control the oscillator frequency range. Value Description 0x00 4MHz 0x01 8MHz 0x10 12MHz 0x11 16MHz Bit 1 – ENABLE: Oscillator Enable Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 241 Value Description The oscillator is disabled. The oscillator is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 242 Number of XOSC Approximate Equivalent Clock Cycles Clock Cycles Time [µs] 1953 3906 7813 15625 1024 31250 2048 62500µs 4096 125000 8192 250000 16384 500000 32768 1000000 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 243 The oscillator is disabled if no peripheral is requesting the clock source. Bit 6 – RUNSTDBY: Run in Standby This bit controls how the XOSC behaves during standby sleep mode, together with the ONDEMAND bit: Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 244 External clock connected on XIN. XOUT can be used as general-purpose I/O. Crystal connected to XIN/XOUT. Bit 1 – ENABLE: Oscillator Enable Value Description The oscillator is disabled. The oscillator is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 245 Chill Cycle is disabled. Bit 7 – ONDEMAND: On Demand Control The On Demand operation mode allows the DFLL to be enabled or disabled depending on peripheral clock requests. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 246 FINE calibration register value will be fixed after a fine lock. Bit 2 – MODE: Operating Mode Selection Value Description The DFLL operates in open-loop operation. The DFLL operates in closed-loop operation. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 247 Due to synchronization, there is delay from updating the register until the peripheral is enabled/disabled. The value written to DFLLCTRL.ENABLE will read back immediately after written. Value Description The DFLL oscillator is disabled. The DFLL oscillator is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 248 Set the value of the Coarse Calibration register. In closed-loop mode, this field is read-only. Bits 9:0 – FINE[9:0]: Fine Value Set the value of the Fine Calibration register. In closed-loop mode, this field is read-only. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 249 This field determines the ratio of the CLK_DFLL output frequency to the CLK_DFLL_REF input frequency. Writing to the MUL bits will cause locks to be lost and the fine calibration value to be reset to its midpoint. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 250 Bit 7 – READREQ: Read Request To be able to read the current value of the DFLLVAL register in closed-loop mode, this bit must be written to '1'. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 251 The software operation of enabling or disabling the DPLL takes a few clock cycles, so the DPLLSYNCBUSY.ENABLE status bit indicates when the DPLL is successfully enabled or disabled. Value Description The DPLL is disabled. The DPLL is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 252 DPLLRATIO bit in the DPLL Synchronization busy register (DPLLSYNCBUSY.DPLLRATIO), will be set. DPLLSYNCBUSY.DPLLRATIO will be cleared when the operation is completed. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 253 DPLL Lock signal is always asserted. Bits 10:8 – LTIME[2:0]: Lock Time These bits select the lock time-out value: Value Name Description Default No time-out. Automatic lock. Reserved Reserved Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 254 These bits select the DPLL filter type: Value Name Description DEFAULT Default filter mode LBFILT Low bandwidth filter HBFILT High bandwidth filter HDFILT High damping filter Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 255 These bits define the output clock prescaler setting. Value Name Description DIV1 DPLL output is divided by 1 DIV2 DPLL output is divided by 2 DIV4 DPLL output is divided by 4 Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 256 Bit 1 – ENABLE: DPLL Enable Synchronization Status Value Description The DPLLCTRLA.ENABLE bit has been synchronized. The DPLLCTRLA.ENABLE bit value has changed and its synchronization is in progress. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 257 The DPLL Lock signal is cleared, when the DPLL is disabled or when the DPLL is trying to reach the target frequency. The DPLL Lock signal is asserted when the desired frequency is reached. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 258: Osc32Kctrl - 32Khz Oscillators Controller

    32.768kHz Ultra Low Power Internal Oscillator (OSCULP32K) – Ultra low power, always-on oscillator – Frequency fine tuning • Calibration value loaded from Flash factory calibration at reset • 1.024kHz clock outputs available Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 259: Block Diagram

    The OSC32KCTRL will continue to operate in any sleep mode where a 32KHz oscillator is running as source clock. The OSC32KCTRL interrupts can be used to wake up the device from sleep modes. Related Links PM – Power Manager on page 188 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 260 The external 32.768kHz crystal must be connected between the XIN32 and XOUT32 pins, along with any required load capacitors. For details on recommended oscillator characteristics and capacitor load, refer to the related links. Related Links Electrical Characteristics on page 1147 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 261: Functional Description

    XOSC32KCTRL. XOSC32KCTRL. Sleep Behavior of XOSC32K and CFD RUNSTDBY ONDEMAND Active or Idle Always run Active or Idle Run if requested by peripheral Standby Always run Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 262 CFD operation is started by writing a '1' to the CFD Enable bit in the External Oscillator Control register (CFDCTRL.CFDEN). After starting or restarting the XOSC32K, the CFD does not detect failure until the Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 263 Event Output. When the CFD is switched to the safe clock, the CFD clock failure will not be output on the Event Output. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 264 SLCD Control register (SLCDCTRL.SLCDSEL). To ensure proper operation, it is highly recommended to first disable the SLCD module before the SLCD clock source is selected. changed. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 265 Writing a '0' to this bit disables the CFD output event. Refer to the Event System chapter for details on configuring the event system. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 266: Register Summary

    Optional Write-Protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write- Protection" property in the register description. Write-protection does not apply to accesses through an external debugger. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 267 Related Links PAC - Peripheral Access Controller on page 50 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 268 Writing a '1' to this bit will clear the XOSC32K Ready Interrupt Enable bit, which disables the XOSC32K Ready interrupt. Value Description The XOSC32K Ready interrupt is disabled. The XOSC32K Ready interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 269 Writing a '1' to this bit will set the XOSC32K Ready Interrupt Enable bit, which enables the XOSC32K Ready interrupt. Value Description The XOSC32K Ready interrupt is disabled. The XOSC32K Ready interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 270 (STATUS.XOSC32KRDY), and will generate an interrupt request if INTENSET.XOSC32KRDY=1. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the XOSC32K Ready interrupt flag. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 271 XOSC32K is not passing failure detection. Bit 0 – XOSC32KRDY: XOSC32K Ready Value Description XOSC32K is not ready. XOSC32K is stable and ready to be used as a clock source. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 272 1.024kHz from 32KHz internal ULP oscillator ULP32K 32.768kHz from 32KHz internal ULP oscillator 0x2, 0x3 Reserved XOSC1K 1.024kHz from 32KHz external oscillator XOSC32K 32.768kHz from 32KHz external crystal oscillator Reserved Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 273 Bit 0 – SLCDSEL: SLCD Clock Source Selection This bit selects the clock source for the SLCD Value Name Description ULP32K 32.768kHz from 32KHz internal ULP oscillator XOSC32K 32.768kHz from external oscillator Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 274 32768 65536 131072 262144 Reserved Note:  Actual Start-Up time is 1 OSCULP32K cycle + 3 XOSC32K cycles. The given time assumes an XTAL frequency of 32.768kHz. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 275 External clock connected on XIN32. XOUT32 can be used as general-purpose I/O. Crystal connected to XIN32/XOUT32. Bit 1 – ENABLE: Oscillator Enable Value Description The oscillator is disabled. The oscillator is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 276 Bit 0 – CFDEN: Clock Failure Detector Enable This bit selects the Clock Failure Detector state. Value Description The CFD is disabled. The CFD is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 277 Value Description Clock Failure Detector Event output is disabled, no event will be generated. Clock Failure Detector Event output is enabled, an event will be generated. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 278 The OSCULP32K configuration is not locked. The OSCULP32K configuration is locked. Bits 12:8 – CALIB[4:0]: Oscillator Calibration These bits control the oscillator calibration. These bits are loaded from Flash Calibration at startup. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 279: Supc - Supply Controller

    Threshold value loaded from NVM User Row at startup – Triggers resets, interrupts, or Battery Backup Power Switch. Action loaded from NVM User – Operating modes: • Continuous mode Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 280: Block Diagram

    I/O Multiplexing and Considerations on page 27 23.5. Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 281 PAC Write-Protection is not available for the following registers: • Interrupt Flag Status and Clear register (INTFLAG) Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual register description. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 282: Functional Description

    The Voltage Scaling Voltage Step field is in the VREG register, VREG.VSVSTEP. The Voltage Scaling Period field is VREG.VSPER. The following waveform shows an example of changing performance level from PL0 to PL2. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 283 The reference voltages are generated by a functional block DETREF inside of the SUPC. DETREF is providing a fixed-voltage source, BANDGAP=1V, and a variable voltage, INTREF. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 284 When the Automatic Power Switch configuration is selected, the Automatic Power Switch Ready bit in the Status register (STATUS.APWSRDY) is set when the Automatic Power Switch is ready to operate. The Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 285 Automatic Power Switch. Leaving backup mode will happen when Main Power is restored and the Battery Backup Power Switch configuration (BBPS.CONF) is set to APWS: When BBPS.WAKEEN=1, the device will leave backup mode and wake up. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 286 BOD33 Level field in the BOD33 register (BOD33.LEVEL). This level is used in all modes except the backup sleep modes. In backup sleep modes, a different voltage reference is used, which is configured by the BOD33.BKUPLEVEL bits. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 287 RESET at each crossing of V , the thresholds for switching RESET on and off are separated (V and V , respectively). BOD- BOD+ Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 288 An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 289 Write-Synchronization starts, and set again when the Write-Synchronization is complete. Writing to the same register while the Write-Synchronization is ongoing (STATUS.B33SRDY is '0') will generate an error without stalling the APB bus. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 290: Register Summary

    BBPS 0x22 23:16 0x23 31:24 0x24 EN[1:0] 0x25 15:8 CLR[1:0] BKOUT 0x26 23:16 SET[1:0] 0x27 31:24 RTCTGL[1:0] 0x28 BKIN[2:0] 0x29 15:8 BKIN 0x2A 23:16 0x2B 31:24 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 291: Register Description

    Some registers require synchronization when read and/or written. Synchronization is denoted by the "Write-Synchronized" or the "Read-Synchronized" property in each individual register description. Refer to Synchronization for details. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 292 Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Automatic Power Switch Ready Interrupt Enable bit, which disables the Automatic Power Switch Ready interrupt. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 293 The BOD33 Ready interrupt is disabled. The BOD33 Ready interrupt is enabled, and an interrupt request will be generated when the BOD33 Ready Interrupt flag is set. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 294 Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Automatic Power Switch Ready Interrupt Enable bit, which enables the Automatic Power Switch Ready interrupt. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 295 The BOD33 Ready interrupt is disabled. The BOD33 Ready interrupt is enabled, and an interrupt request will be generated when the BOD33 Ready Interrupt flag is set. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 296 This flag is set on a zero-to-one transition of the Voltage Regulator Ready bit in the Status register (STATUS.VREGRDY) and will generate an interrupt request if INTENSET.VREGRDY=1. Writing a '0' to this bit has no effect. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 297 Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the BOD33 Ready interrupt flag. The BOD33 can be enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 298 Bit 9 – APWSRDY: Automatic Power Switch Ready Value Description The Automatic Power Switch is not ready. The Automatic Power Switch is ready. Bit 8 – VREGRDY: Voltage Regulator Ready Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 299 BOD33 has detected that the I/O power supply is going below the BOD33 reference value. Bit 0 – BOD33RDY: BOD33 Ready The BOD33 can be enabled at start-up from NVM User Row. Value Description BOD33 is not ready. BOD33 is ready. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 300 OSCULP32K 1KHz output. Value Name Description DIV2 Divide clock by 2 DIV4 Divide clock by 4 DIV8 Divide clock by 8 DIV16 Divide clock by 16 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 301 Bit 6 – RUNSTDBY: Run in Standby This bit is not synchronized. Value Description In standby sleep mode, the BOD33 is disabled. In standby sleep mode, the BOD33 is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 302 Bit 1 – ENABLE: Enable This bit is loaded from NVM User Row at start-up. This bit is not enable-protected. Value Description BOD33 is disabled. BOD33 is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 303 The voltage regulator in Low power mode has the highest efficiency and supports a limited VDD range (2.5V to 3.6V). Bit 6 – RUNSTDBY: Run in Standby Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 304 The voltage regulator in active mode is a buck converter. Bit 1 – ENABLE: Enable Value Description The voltage regulator is disabled. The voltage regulator is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 305 The voltage reference is enabled when a peripheral is requesting it. The voltage reference is disabled if no peripheral is requesting it. Bit 6 – RUNSTDBY: Run In Standby The bit controls how the voltage reference behaves during standby sleep mode. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 306 Bit 2 – VREFOE: Voltage Reference Output Enable Value Description The Voltage Reference output is not available as an ADC input channel. The Voltage Reference output is routed to an ADC input channel. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 307 The power switch is handled by the Automatic Power Switch. FORCED The backup domain is always supplied by Battery Backup Power. BOD33 The power switch is handled by the BOD33. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 308 Writing a '0' to a bit has no effect. Writing a '1' to a bit will clear the corresponding output. Reading this bit returns '0'. Bits 1:0 – EN[1:0]: Enable Output Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 309 Value Description The output is not enabled. The output is enabled and driven by the SUPC. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 310 If BKOUT.EN[0]=1, BKIN[1] will give the input value of the OUT[0] pin BKIN[2] OUT[1] If BKOUT.EN[1]=1, BKIN[2] will give the input value of the OUT[1] pin Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 311: Wdt - Watchdog Timer

    Selectable time-out periods – From 8 cycles to 16,384 cycles in Normal mode – From 16 cycles to 32,768 cycles in Window mode • Always-On capability Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 312: Block Diagram

    This variation must be kept in mind when designing software that uses the WDT to ensure that the time-out periods used are valid for all devices. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 313: Functional Description

    Early Warning interrupt generation. The description for each of the basic modes is given below. The settings in the Control A register (CTRLA) and the Interrupt Enable register (handled by INTENCLR/ INTENSET) determine the mode of operation: Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 314 WDT is disabled by writing a '0' to CTRLA.ENABLE. The WDT can be disabled only if the Always-On bit in the Control A register (CTRLA.ALWAYSON) is '0'. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 315 Interrupt Enable register (INTENSET.EW) must be written to '1'. The Early Warning Interrupt is disabled again by writing a '1' to the Early Warning Interrupt bit in the Interrupt Enable Clear (INTENCLR.EW) register. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 316 44 Interrupt Line Mapping on page 44 PM – Power Manager on page 188 Sleep Mode Controller on page 191 24.6.5. Events Not applicable. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 317 Interrupt Enable Mode Always-on and normal mode Always-on and normal mode with Early Warning interrupt Always-on and window mode Always-on and window mode with Early Warning interrupt Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 318 CLK_WDT_OSC clock cycles after the start of the time-out period. The time-out system reset is generated 32 CLK_WDT_OSC clock cycles after the start of the watchdog time- out period. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 319: Register Summary

    Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 320 Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. This bit is not Enable-Protected. This bit is loaded from NVM User Row at startup. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 321 Value Description The WDT is disabled. The WDT is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 322 In Window mode operation, these bits define the open window period. These bits are loaded from NVM User Row at startup. Value Name Description CYC8 8 clock cycles CYC16 16 clock cycles CYC32 32 clock cycles Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 323 512 clock cycles CYC1024 1024 clock cycles CYC2048 2048 clock cycles CYC4096 4096 clock cycles CYC8192 8192 clock cycles CYC16384 16384 clock cycles 0xC - 0xF - Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 324 512 clock cycles CYC1024 1024 clock cycles CYC2048 2048 clock cycles CYC4096 4096 clock cycles CYC8192 8192 clock cycles CYC16384 16384 clock cycles 0xC - 0xF - Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 325 Writing a '1' to this bit clears the Early Warning Interrupt Enable bit, which disables the Early Warning interrupt. Value Description The Early Warning interrupt is disabled. The Early Warning interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 326 Writing a '1' to this bit sets the Early Warning Interrupt Enable bit, which enables the Early Warning interrupt. Value Description The Early Warning interrupt is disabled. The Early Warning interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 327 This flag is set when an Early Warning interrupt occurs, as defined by the EWOFFSET bit group in EWCTRL. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Early Warning interrupt flag. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 328 Bit 2 – WEN: Window Enable Synchronization Busy Value Description Write synchronization of the CTRLA.WEN bit is complete. Write synchronization of the CTRLA.WEN bit is ongoing. Bit 1 – ENABLE: Enable Synchronization Busy Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 329 Value Description Write synchronization of the CTRLA.ENABLE bit is complete. Write synchronization of the CTRLA.ENABLE bit is ongoing. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 330 Watchdog Timer and the complete time-out sequence (first TO then TO ) is restarted. WDTW In both modes, writing any other value than 0xA5 will issue an immediate system Reset. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 331: Rtc - Real-Time Counter

    2 general purpose registers • 8 backup registers with retention capability • Tamper Detection – Timestamp on event or up to 5 inputs with debouncing – Active layer protection Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 332: Block Diagram

    PRESCALER COUNT Periodic Events CMPn COMPn Figure 25-3. RTC Block Diagram (Mode 2 — Clock/Calendar) 0x00000000 MATCHCLR CLK_RTC_OSC LK_RTC_CNT OSC32KCTRL CLOCK PRESCALER ALARMn MASKn Periodic Events ALARMn Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 333: Signal Description

    The RTC will be reset only at power-on (POR) or by setting the Software Reset bit in the Control A register (CTRLA.SWRST=1). Related Links PM – Power Manager on page 188 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 334 Write-protection does not apply to accesses through an external debugger. Refer to the PAC - Peripheral Access Controller for details. Related Links PAC - Peripheral Access Controller on page 50 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 335: Functional Description

    Note:  In Clock/Calendar mode, the prescaler must be configured to provide a 1Hz clock to the counter for correct operation. The frequency of the RTC clock (CLK_RTC_CNT) is given by the following formula: Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 336 1Hz clock to the counter for correct operation in this mode. The time and date can be read from or written to the Clock Value register (CLOCK) in a 32-bit time/date format. Time is represented as: Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 337 Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 338 The periodic events can also wake up the CPU through the interrupt function of the Event System. In this case, the event must be enabled and connected to an event channel with its interrupt enabled. See Event System for more information. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 339 CLK_RTC_OSC EVCTRL.PEREOn bit. For example, PER0 will generate an event every eight CLK_RTC_OSC cycles, PER1 every 16 cycles, etc. This is shown in the figure below. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 340 Wake: A transition on INn matching TAMPCTRL.TAMPLVLn will be detected and the tamper interrupt flag (INTFLAG.TAMPER) will be set. The RTC value will not be captured in the TIMESTAMP register Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 341 3 consecutive CLK_RTC_DEB periods. Signal level is determined by majority-rule (LLL, LLH, LHL, HLL = '0' and LHH, HLH, HHL, HHH = '1'). Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 342 TAMLVL=0 CLK_RTC CLK_RTC_DEB Whenever an edge is detected, input must be stable for 4 consecutive CLK_RTC_DEB in order for edge to be considered valid TAMLVL=1 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 343 IN shift 1 IN shift 2 MAJORITY3 1-to-0 transition TAMLVL=0 CLK_RTC CLK_RTC_DEB IN shift 0 IN shift 1 IN shift 2 MAJORITY3 0-to-1 transition TAMLVL=1 Related Links Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 344 OUT. Therefore up to one half of a CLK_RTC period is available for propagation delay through the trace. Related Links Tamper Detection on page 340 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 345: Register Summary - Count32

    0x20 COMP[7:0] 0x21 15:8 COMP[15:8] COMP0 0x22 23:16 COMP[23:16] 0x23 31:24 COMP[31:24] 0x24 Reserved 0x3F 0x40 GP[7:0] 0x41 15:8 GP[15:8] 0x42 23:16 GP[23:16] 0x43 31:24 GP[31:24] Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 346 31:24 BKUP[31:24] 0x90 BKUP[7:0] 0x91 15:8 BKUP[15:8] BKUP4 0x92 23:16 BKUP[23:16] 0x93 31:24 BKUP[31:24] 0x94 BKUP[7:0] 0x95 15:8 BKUP[15:8] BKUP5 0x96 23:16 BKUP[23:16] 0x97 31:24 BKUP[31:24] Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 347: Register Description - Count32

    Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 348 (CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These bits are not synchronized. Value Name Description CLK_RTC_CNT = GCLK_RTC/1 DIV1 CLK_RTC_CNT = GCLK_RTC/1 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 349 Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. Value Description The peripheral is disabled The peripheral is enabled Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 350 Due to synchronization there is a delay between writing CTRLA.SWRST and until the reset is complete. CTRLA.SWRST will be cleared when the reset is complete. Value Description There is not reset operation ongoing The reset operation is ongoing Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 351 CLK_RTC_DEB = CLK_RTC / 4 DIV8 CLK_RTC_DEB = CLK_RTC / 8 DIV16 CLK_RTC_DEB = CLK_RTC / 16 DIV32 CLK_RTC_DEB = CLK_RTC / 32 DIV64 CLK_RTC_DEB = CLK_RTC / 64 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 352 The tamper input debouncers match majority two of three values. Bit 0 – GP0EN: General Purpose 0 Enable Value Description COMP0 compare function enabled. GP0/GP1 disabled. COMP0 compare function disabled. GP0/GP1 enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 353 Tamper event output is disabled and will not be generated. Tamper event output is enabled and will be generated for every tamper input. Bit 8 – CMPEO0: Compare 0 Event Output Enable Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 354 Bits 7:0 – PEREOn: Periodic Interval n Event Output Enable [n = 7..0] Value Description Periodic Interval n event is disabled and will not be generated. Periodic Interval n event is enabled and will be generated. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 355 The Compare 0 interrupt is enabled. Bits 7:0 – PERn: Periodic Interval n Interrupt Enable [n = 7..0] Writing a '0' to this bit has no effect. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 356 Writing a '1' to this bit will clear the Periodic Interval n Interrupt Enable bit, which disables the Periodic Interval n interrupt. Value Description Periodic Interval n interrupt is disabled. Periodic Interval n interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 357 The Compare 0 interrupt is enabled. Bits 7:0 – PERn: Periodic Interval n Interrupt Enable [n = 7..0] Writing a '0' to this bit has no effect. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 358 Writing a '1' to this bit will set the Periodic Interval n Interrupt Enable bit, which enables the Periodic Interval n interrupt. Value Description Periodic Interval n interrupt is disabled. Periodic Interval n interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 359 This flag is set on the 0-to-1 transition of prescaler bit [n+2], and an interrupt request will be generated if INTENCLR/SET.PERx is one. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Periodic Interval n interrupt flag. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 360 The RTC is halted when the CPU is halted by an external debugger. The RTC continues normal operation when the CPU is halted by an external debugger. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 361 Bit 5 – COMP0: Compare 0 Synchronization Busy Status Value Description Write synchronization for COMP0 register is complete. Write synchronization for COMP0 register is ongoing. Bit 3 – COUNT: Count Value Synchronization Busy Status Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 362 Read/write synchronization for CTRLA.ENABLE bit is ongoing. Bit 0 – SWRST: Software Reset Synchronization Busy Status Value Description Read/write synchronization for CTRLA.SWRST bit is complete. Read/write synchronization for CTRLA.SWRST bit is ongoing. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 363 These bits define the amount of correction applied to the RTC prescaler. Value Description Correction is disabled and the RTC frequency is unchanged. 1 - 127 The RTC frequency is adjusted according to the value. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 364 Access Reset COUNT[15:8] Access Reset COUNT[7:0] Access Reset Bits 31:0 – COUNT[31:0]: Counter Value These bits define the value of the 32-bit RTC counter in mode 0. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 365 Compare 0 interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMP0) is set on the next counter cycle, and the counter value is cleared if CTRLA.MATCHCLR is '1'. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 366   GP[31:24] Access Reset GP[23:16] Access Reset GP[15:8] Access Reset GP[7:0] Access Reset Bits 31:0 – GP[31:0]: General Purpose These bits are for user-defined general purpose use. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 367 Bits 10:9 – IN4ACT[1:0]: Tamper Input 4 Action These bits determine the action taken by Tamper Input IN4. Value Name Description Off (Disabled) WAKE Wake and set Tamper flag Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 368 Bits 2:1 – IN0ACT[1:0]: Tamper Input 0 Action These bits determine the action taken by Tamper Input IN0. Value Name Description Off (Disabled) WAKE Wake and set Tamper flag Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 369 Value Name Description CAPTURE Capture timestamp and set Tamper flag ACTL Compare INn to OUT. When a mismatch occurs, capture timestamp and set Tamper flag Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 370 Access Reset COUNT[7:0] Access Reset Bits 31:0 – COUNT[31:0]: Count Timestamp Value The 32-bit value of COUNT is captured by the TIMESTAMP when a tamper condition occurs Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 371 Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the tamper detection bit. Value Description A tamper input condition has not been detected on INn pin A tamper input condition has been detected in INn pin Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 372 Reset BKUP[23:16] Access Reset BKUP[15:8] Access Reset BKUP[7:0] Access Reset Bits 31:0 – BKUP[31:0]: Backup These bits are user-defined for general purpose use in the Backup domain. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 373: Register Summary - Count16

    COMP[15:8] 0x24 Reserved 0x3F 0x40 GP[7:0] 0x41 15:8 GP[15:8] 0x42 23:16 GP[23:16] 0x43 31:24 GP[31:24] 0x44 GP[7:0] 0x45 15:8 GP[15:8] 0x46 23:16 GP[23:16] 0x47 31:24 GP[31:24] Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 374 31:24 BKUP[31:24] 0x94 BKUP[7:0] 0x95 15:8 BKUP[15:8] BKUP5 0x96 23:16 BKUP[23:16] 0x97 31:24 BKUP[31:24] 0x98 BKUP[7:0] 0x99 15:8 BKUP[15:8] BKUP6 0x9A 23:16 BKUP[23:16] 0x9B 31:24 BKUP[31:24] Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 375: 25.10. Register Description - Count16

    Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 376 These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock (CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These bits are not synchronized. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 377 Writing a '1' to this bit resets all registers in the RTC (except DBGCTRL) to their initial state, and the RTC will be disabled. Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 378 Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST will be cleared when the reset is complete. Value Description There is not reset operation ongoing The reset operation is ongoing Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 379 CLK_RTC_DEB = CLK_RTC / 4 DIV8 CLK_RTC_DEB = CLK_RTC / 8 DIV16 CLK_RTC_DEB = CLK_RTC / 16 DIV32 CLK_RTC_DEB = CLK_RTC / 32 DIV64 CLK_RTC_DEB = CLK_RTC / 64 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 380 The tamper input debouncers match majority two of three values. Bit 0 – GP0EN: General Purpose 0 Enable Value Description COMP0 compare function enabled. GP0/GP1 disabled. COMP0 compare function disabled. GP0/GP1 enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 381 Tamper event output is disabled, and will not be generated. Tamper event output is enabled, and will be generated for every tamper input. Bits 10:9 – ALARMEOn: Alarm n Event Output Enable Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 382 Periodic Interval n event is disabled and will not be generated. [n = 7..0] Periodic Interval n event is enabled and will be generated. [n = 7..0] Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 383 Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Periodic Interval n Interrupt Enable bit, which disables the Periodic Interval n interrupt. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 384 Value Description Periodic Interval n interrupt is disabled. Periodic Interval n interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 385 Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Periodic Interval n Interrupt Enable bit, which enables the Periodic Interval n interrupt. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 386 Value Description Periodic Interval n interrupt is disabled. Periodic Interval n interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 387 This flag is set on the 0-to-1 transition of prescaler bit [n+2], and an interrupt request will be generated if INTENCLR/SET.PERx is one. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Periodic Interval n interrupt flag. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 388 The RTC is halted when the CPU is halted by an external debugger. The RTC continues normal operation when the CPU is halted by an external debugger. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 389 Bit 4 – PER: Period Synchronization Busy Status Value Description Write synchronization for PER register is complete. Write synchronization for PER register is ongoing. Bit 3 – COUNT: Count Value Synchronization Busy Status Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 390 Read/write synchronization for CTRLA.ENABLE bit is ongoing. Bit 0 – SWRST: Software Reset Synchronization Busy Status Value Description Read/write synchronization for CTRLA.SWRST bit is complete. Read/write synchronization for CTRLA.SWRST bit is ongoing. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 391 These bits define the amount of correction applied to the RTC prescaler. Value Description Correction is disabled and the RTC frequency is unchanged. 1 - 127 The RTC frequency is adjusted according to the value. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 392   COUNT[15:8] Access Reset COUNT[7:0] Access Reset Bits 15:0 – COUNT[15:0]: Counter Value These bits define the value of the 16-bit RTC counter in COUNT16 mode (CTRLA.MODE=1). Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 393   PER[15:8] Access Reset PER[7:0] Access Reset Bits 15:0 – PER[15:0]: Counter Period These bits define the value of the 16-bit RTC period in COUNT16 mode (CTRLA.MODE=1). Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 394 The 16-bit value of COMP0 is continuously compared with the 16-bit COUNT value. When a match occurs, the Compare 0 interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMP0) is set on the next counter cycle. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 395 The 16-bit value of COMPn is continuously compared with the 16-bit COUNT value. When a match occurs, the Compare n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn) is set on the next counter cycle. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 396   GP[31:24] Access Reset GP[23:16] Access Reset GP[15:8] Access Reset GP[7:0] Access Reset Bits 31:0 – GP[31:0]: General Purpose These bits are for user-defined general purpose use. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 397 Bits 10:9 – IN4ACT[1:0]: Tamper Input 4 Action These bits determine the action taken by Tamper Input IN4. Value Name Description Off (Disabled) WAKE Wake and set Tamper flag Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 398 Bits 2:1 – IN0ACT[1:0]: Tamper Input 0 Action These bits determine the action taken by Tamper Input IN0. Value Name Description Off (Disabled) WAKE Wake and set Tamper flag Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 399 Value Name Description CAPTURE Capture timestamp and set Tamper flag ACTL Compare INn to OUT. When a mismatch occurs, capture timestamp and set Tamper flag Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 400 Access Reset COUNT[7:0] Access Reset Bits 15:0 – COUNT[15:0]: Count Timestamp Value The 16-bit value of COUNT is captured by the TIMESTAMP when a tamper condition occurs. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 401 Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the tamper detection bit. Value Description A tamper input condition has not been detected on INn pin A tamper input condition has been detected in INn pin Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 402 Reset BKUP[23:16] Access Reset BKUP[15:8] Access Reset BKUP[7:0] Access Reset Bits 31:0 – BKUP[31:0]: Backup These bits are user-defined for general purpose use in the Backup domain. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 403: 25.11. Register Summary - Clock

    0x22 23:16 MONTH[1:0] DAY[4:0] HOUR[4:4] 0x23 31:24 YEAR[5:0] MONTH[3:2] 0x24 MASK SEL[2:0] 0x25 Reserved 0x3F 0x40 GP[7:0] 0x41 15:8 GP[15:8] 0x42 23:16 GP[23:16] 0x43 31:24 GP[31:24] Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 404 31:24 BKUP[31:24] 0x90 BKUP[7:0] 0x91 15:8 BKUP[15:8] BKUP4 0x92 23:16 BKUP[23:16] 0x93 31:24 BKUP[31:24] 0x94 BKUP[7:0] 0x95 15:8 BKUP[15:8] BKUP5 0x96 23:16 BKUP[23:16] 0x97 31:24 BKUP[31:24] Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 405: 25.12. Register Description - Clock

    Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 406 (CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These bits are not synchronized. Value Name Description CLK_RTC_CNT = GCLK_RTC/1 DIV1 CLK_RTC_CNT = GCLK_RTC/1 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 407 Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/ disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 408 Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST will be cleared when the reset is complete. Value Description There is not reset operation ongoing The reset operation is ongoing Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 409 CLK_RTC_DEB = CLK_RTC / 4 DIV8 CLK_RTC_DEB = CLK_RTC / 8 DIV16 CLK_RTC_DEB = CLK_RTC / 16 DIV32 CLK_RTC_DEB = CLK_RTC / 32 DIV64 CLK_RTC_DEB = CLK_RTC / 64 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 410 COMP1 compare function disabled. GP2 enabled. Bit 0 – GP0EN: General Purpose 0 Enable Value Description COMP0 compare function enabled. GP0 disabled. COMP0 compare function disabled. GP0 enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 411 Tamper event output is disabled, and will not be generated Tamper event output is enabled, and will be generated for every tamper input. Bit 8 – ALARMO0: Alarm 0 Event Output Enable Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 412 Bits 7:0 – PEREOn: Periodic Interval n Event Output Enable [n = 7..0] Value Description Periodic Interval n event is disabled and will not be generated. Periodic Interval n event is enabled and will be generated. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 413 Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Periodic Interval n Interrupt Enable bit, which disables the Periodic Interval n interrupt. Value Description Periodic Interval n interrupt is disabled. Periodic Interval n interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 414 Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Periodic Interval n Interrupt Enable bit, which enables the Periodic Interval n interrupt. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 415 Value Description Periodic Interval n interrupt is disabled. Periodic Interval n interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 416 This flag is set on the 0-to-1 transition of prescaler bit [n+2], and an interrupt request will be generated if INTENCLR/SET.PERx is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Periodic Interval n interrupt flag. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 417 The RTC is halted when the CPU is halted by an external debugger. The RTC continues normal operation when the CPU is halted by an external debugger. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 418 Bit 11 – MASK0: Mask 0 Synchronization Busy Status Value Description Write synchronization for MASK0 register is complete. Write synchronization for MASK0 register is ongoing. Bit 5 – ALARM0: Alarm 0 Synchronization Busy Status Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 419 Read/write synchronization for CTRLA.ENABLE bit is ongoing. Bit 0 – SWRST: Software Reset Synchronization Busy Status Value Description Read/write synchronization for CTRLA.SWRST bit is complete. Read/write synchronization for CTRLA.SWRST bit is ongoing. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 420 These bits define the amount of correction applied to the RTC prescaler. Value Description Correction is disabled and the RTC frequency is unchanged. 1 - 127 The RTC frequency is adjusted according to the value. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 421 When CTRLA.CLKREP=0, the Hour bit group is in 24-hour format, with values 0-23. When CTRLA.CLKREP=1, HOUR[3:0] has values 1-12, and HOUR[4] represents AM (0) or PM (1). Bits 11:6 – MINUTE[5:0]: Minute 0 – 59 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 422 Bits 5:0 – SECOND[5:0]: Second 0 – 59 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 423 The alarm minute. Minutes are matched only if MASK.SEL is greater than 1. Bits 5:0 – SECOND[5:0]: Second The alarm second. Seconds are matched only if MASK.SEL is greater than 0. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 424 Match seconds, minutes, hours, and days only MMDDHHMMSS Match seconds, minutes, hours, days, and months only YYMMDDHHMMSS Match seconds, minutes, hours, days, months, and years Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 425   GP[31:24] Access Reset GP[23:16] Access Reset GP[15:8] Access Reset GP[7:0] Access Reset Bits 31:0 – GP[31:0]: General Purpose These bits are for user-defined general purpose use. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 426 Bits 10:9 – IN4ACT[1:0]: Tamper Input 4 Action These bits determine the action taken by Tamper Input IN4. Value Name Description Off (Disabled) WAKE Wake and set Tamper flag Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 427 Bits 2:1 – IN0ACT[1:0]: Tamper Input 0 Action These bits determine the action taken by Tamper Input IN0. Value Name Description Off (Disabled) WAKE Wake and set Tamper flag Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 428 Value Name Description CAPTURE Capture timestamp and set Tamper flag ACTL Compare INn to OUT. When a mismatch occurs, capture timestamp and set Tamper flag Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 429 The minute value is captured by the TIMESTAMP when a tamper condition occurs. Bits 10:5 – SECOND[5:0]: Second The second value is captured by the TIMESTAMP when a tamper condition occurs. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 430 Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the tamper detection bit. Value Description A tamper input condition has not been detected on INn pin A tamper input condition has been detected in INn pin Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 431 Reset BKUP[23:16] Access Reset BKUP[15:8] Access Reset BKUP[7:0] Access Reset Bits 31:0 – BKUP[31:0]: Backup These bits are user-defined for general purpose use in the Backup domain. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 432: Dmac - Direct Memory Access Controller

    Dedicated requests from peripherals • SRAM based transfer descriptors – Single transfer using one descriptor – Multi-buffer or circular buffer modes by linking multiple descriptors • Up to 16channels Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 433 Dedicated Write-Back memory section for each channel to store ongoing descriptor transfer • CRC polynomial software selectable to – CRC-16 (CRC-CCITT) ® – CRC-32 (IEEE 802.3) Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 434: Block Diagram

    PM – Power Manager on page 188 26.5.3. Clocks The DMAC bus clock (CLK_DMAC_APB) must be configured and enabled in the Main Clock module before using the DMAC. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 435: Functional Description

    DMAC are called transactions, and these transactions can be split into smaller data transfers. Figure 'DMA Transfer Sizes' shows the relationship between the different transfer sizes: Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 436 The following DMAC bit is enable-protected, meaning that it can only be written when both the DMAC and CRC are disabled (CTRL.DMAENABLE=0 and CTRL.CRCENABLE=0): • Software Reset bit in Control register (CTRL.SWRST) Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 437 If CRC calculation is needed, the CRC engine must be configured before it is enabled, as outlined by the following steps: • The CRC input source must selected by writing the CRC Input Source bit group in the CRC Control register (CRCCTRL.CRCSRC) Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 438 The figure below shows an example of linked descriptors on DMA channel 0. For further details on linked descriptors, refer to Linked Descriptors. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 439 When the arbiter has granted a DMA channel access to the DMAC, the corresponding bit PENDCH.PENDCHx will be cleared. See also the following figure. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 440 When using the static arbitration there is a risk of high channel numbers never being granted access as the active channel. This can be avoided using a dynamic arbitration scheme. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 441 Once the arbiter has granted a DMA channel access as the active channel (refer to Figure 26-1) the transfer descriptor for the DMA channel will be fetched from SRAM using the fetch bus, and stored in the Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 442 The trigger actions can also be configured to generate a request for a beat transfer (CHCTRLB.TRIGACT=0x2) or transaction transfer (CHCTRLB.TRIGACT=0x3) instead of a block transfer (CHCTRLB.TRIGACT=0x0). Figure 26-7 shows an example where triggers are used with two linked block descriptors. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 443 Step Selection bit in the Block Transfer Control register (BTCTRL.STEPSEL=1) and writing the desired step size in the Address Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 444 START • BTCNT is the initial number of beats remaining in the block transfer Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 445 Modifying a Descriptor in a List In order to add descriptors to a linked list, the following actions must be performed: Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 446 Command bit field of Channel Control B register (CHCTRLB.CMD). After the ongoing burst transfer is completed, the channel operation is suspended and the suspend command is automatically cleared. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 447 Channel Event Input Enable bit in the Channel Control B register (CHCTRLB.EVIE) must be written to '1'. Refer also to Events. Table 26-1. Event Input Action Action CHCTRLB.EVACT CHCTRLB.TRGSRC None NOACT Normal Transfer TRIG DISABLE Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 448 CHSTATUS.PEND and PENDCH.PENDCHn are set. A software trigger will now trigger a transfer. The figure below shows an example where the peripheral beat transfer is started by a conditional strobe event action. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 449 A software trigger will trigger a transfer. The figure below shows an example where conditional event block transfer is started with peripheral beat trigger requests. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 450 The figure Figure 26-15 shows an example where the event output generation is enabled in the first block transfer, and disabled in the second block. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 451 CRC-32 (IEEE 802.3). Typically, applying CRC-n (CRC-16 or CRC-32) to a data block of arbitrary length will detect any single alteration that is ≤n bits in length, and will detect the fraction 1-2-n of all longer error bursts. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 452 CRC engine will operate on the input data in a byte by byte manner. Figure 26-16. CRC Generator Block Diagram DMAC Channels CRCDATAIN CRCCTRL CRC-16 CRC-32 crc32 CHECKSUM bit-reverse + complement Checksum read Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 453 Note:  Interrupts must be globally enabled for interrupt requests to be generated. Related Links Nested Vector Interrupt Controller on page 44 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 454 Event System. Note:  In standby sleep mode, the DMAC can only access RAM when it is not back biased (PM.STDBYCFG.BBIASxx=0x0) 26.6.8. Synchronization Not applicable. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 455: Register Summary

    0x2B 31:24 0x2C PENDCH7 PENDCH6 PENDCH5 PENDCH4 PENDCH3 PENDCH2 PENDCH1 PENDCH0 0x2D 15:8 PENDCH15 PENDCH14 PENDCH13 PENDCH12 PENDCH11 PENDCH10 PENDCH9 PENDCH8 PENDCH 0x2E 23:16 0x2F 31:24 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 456: Register Description

    Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 457 CRCENABLE are '0') resets all registers in the DMAC (except DBGCTRL) to their initial state. If either the DMAC or CRC module is enabled, the Reset request will be ignored and the DMAC will return an access error. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 458 These bits are not enable-protected. Value Description Transfer requests for Priority level x will not be handled. Transfer requests for Priority level x will be handled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 459 DMA channel 6 0x27 DMA channel 7 0x28 DMA channel 8 0x29 DMA channel 9 0x2A DMA channel 10 0x2B DMA channel 11 0x2C DMA channel 12 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 460 These bits define the size of the data transfer for each bus access when the CRC is used with I/O interface. Value Name Description BYTE 8-bit bus transfer HWORD 16-bit bus transfer WORD 32-bit bus transfer Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 461 Value Name Description Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 462 These bits store the data for which the CRC checksum is computed. A new CRC Checksum is ready (CRCBEAT+ 1) clock cycles after the CRCDATAIN register is written. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 463 Access Reset Bits 31:0 – CRCCHKSUM[31:0]: CRC Checksum These bits store the generated CRC result. The 16 MSB bits are always read zero when CRC-16 is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 464 This register bit cannot be cleared by the application when the CRC is used with a DMA channel. This bit is set when a source configuration is selected and as long as the source is using the CRC module. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 465 The DMAC is halted when the CPU is halted by an external debugger. The DMAC continues normal operation when the CPU is halted by an external debugger. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 466 These bits define the memory priority access during the write-back operation. WRBQOS[1:0] Name Description DISABLE Background (no sensitive operation) Sensitive Bandwidth MEDIUM Sensitive Latency HIGH Critical Latency Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 467 Writing a '1' to this bit will generate a DMA software trigger on channel x, if CHSTATUS.PEND=0 for channel x. CHSTATUS.PEND will be set and SWTRIGn will remain cleared. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 468 Bit 23 – RRLVLEN2: Level 2 Round-Robin Arbitration Enable This bit controls which arbitration scheme is selected for DMA channels with priority level 2. For details on arbitration schemes, refer to Arbitration. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 469 This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN0 written to '0'). Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 470 These bits store the lowest channel number with pending interrupts. The number is valid if Suspend (SUSP), Transfer Complete (TCMPL) or Transfer Error (TERR) bits are set. The Channel ID field is Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 471 When the bits are written, indirect access to the corresponding Channel Interrupt Flag register is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 472 This bit is set when Channel n has a pending interrupt/the interrupt request is received. This bit is cleared when the corresponding Channel n interrupts are disabled or the interrupts sources are cleared. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 473 This bit is cleared when the channel trigger action for DMA channel n is complete, when a bus error for DMA channel n is detected, or when DMA channel n is disabled. This bit is set when DMA channel n starts a DMA transfer. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 474 DMA channel n is detected or when DMA channel n is disabled. For details on trigger action settings, refer to CHCTRLB.TRIGACT. This bit is set when a transfer is pending on DMA channel n. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 475 This bit is set when a level-x channel trigger request is executing or pending. This bit is cleared when no request is pending or being executed. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 476 Reset BASEADDR[7:0] Access Reset Bits 31:0 – BASEADDR[31:0]: Descriptor Memory Base Address These bits store the Descriptor memory section base address. The value must be 128-bit aligned. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 477 Access Reset WRBADDR[7:0] Access Reset Bits 31:0 – WRBADDR[31:0]: Write-Back Memory Base Address These bits store the Write-Back memory base address. The value must be 128-bit aligned. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 478 These bits define the channel number that will be affected by the channel registers (CH*). Before reading or writing a channel register, the channel ID bit group must be written first. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 479 (ENABLE=0). Writing a '1' to this bit will be ignored as long as ENABLE=1. This bit is automatically cleared when the reset is completed. Value Description There is no reset operation ongoing. The reset operation is ongoing. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 480 Bits 23:22 – TRIGACT[1:0]: Trigger Action These bits define the trigger action used for a transfer. TRIGACT[1:0] Name Description BLOCK One trigger required for each block transfer Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 481 TC1 MC0 TC1 Match/Compare 0 Trigger 0x18 TC1 MC1 TC1 Match/Compare 1 Trigger 0x19 TC2 OVF TC2 Overflow Trigger 0x1A TC2 MC0 TC2 Match/Compare 0 Trigger Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 482 This bit is available only for the least significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 483 Normal Transfer and Conditional Transfer on Strobe trigger CTRIG Conditional transfer trigger CBLOCK Conditional block transfer SUSPEND Channel suspend operation RESUME Channel resume operation SSKIP Skip next block suspend action Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 484 Writing a '1' to this bit will clear the Channel Transfer Error Interrupt Enable bit, which disables the Channel Transfer Error interrupt. Value Description The Channel Transfer Error interrupt is disabled. The Channel Transfer Error interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 485 Writing a '1' to this bit will set the Channel Transfer Error Interrupt Enable bit, which enables the Channel Transfer Error interrupt. Value Description The Channel Transfer Error interrupt is disabled. The Channel Transfer Error interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 486 Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Transfer Error interrupt flag for the corresponding channel. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 487 For details on trigger action settings, refer to CHCTRLB.TRIGACT. This bit is set when a transfer is pending on the DMA channel, as soon as the transfer request is received. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 488: Register Summary - Sram

    Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 489 Bit 11 – DSTINC: Destination Address Increment Enable Writing a '0' to this bit will disable the destination address incrementation. The address will be kept fixed during the data transfer. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 490 SUSPEND Channel suspend operation is completed BOTH Both channel suspend operation and block interrupt Bits 2:1 – EVOSEL[1:0]: Event Output Selection These bits define the event output selection. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 491 The bit is automatically cleared in the Write-Back memory section when channel is aborted, when an error is detected during the block transfer, or when the block transfer is completed. Value Description The descriptor is not valid. The descriptor is valid. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 492 DMA channel when the DMA channel loses priority, is suspended or gets disabled. The DMA channel can be disabled by a complete transfer, a transfer error or by software. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 493 Access Reset Bits 31:0 – SRCADDR[31:0]: Transfer Source Address This bit group holds the source address corresponding to the last beat transfer address in the block transfer. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 494 Access Reset Bits 31:0 – DSTADDR[31:0]: Transfer Destination Address This bit group holds the destination address corresponding to the last beat transfer address in the block transfer. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 495 This bit group holds the SRAM address of the next descriptor. The value must be 128-bit aligned. If the value of this SRAM register is 0x00000000, the transaction will be terminated when the DMAC tries to load the next transfer descriptor. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 496: Eic - External Interrupt Controller

    Block Diagram Figure 27-1. EIC Block Diagram SENSEx[2:0] FILTENx intreq_extint Interrupt EXTINTx inwake_extint Edge/Level Wake Filter Detection evt_extint Event NMISENSE[2:0] NMIFILTEN intreq_nmi Interrupt Edge/Level Filter Detection inwake_nmi Wake Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 497: Signal Description

    MCLK – Main Clock on page 141 Peripheral Clock Masking on page 145 GCLK - Generic Clock Controller on page 121 OSC32KCTRL – 32KHz Oscillators Controller on page 258 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 498: Functional Description

    The EIC detects edge or level condition to generate interrupts to the CPU interrupt controller or events to the Event System. Each external interrupt pin (EXTINT) can be filtered using majority vote filtering, clocked by GCLK_EIC or by CLK_ULP32K. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 499 '1'. The majority vote filter samples the external pin three times with GCLK_EIC or CLK_ULP32K and outputs the value when two or more samples are equal. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 500 Four GCLK_EIC/CLK_ULP32K periods + five CLK_EIC_APB periods Edge with filter Six GCLK_EIC/CLK_ULP32K periods + five CLK_EIC_APB periods Related Links GCLK - Generic Clock Controller on page 121 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 501 The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the EIC is reset. See the INTFLAG register for details on how to clear interrupt flags. The EIC has one common Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 502 Software Reset bit in control register (CTRLA.SWRST) • Enable bit in control register (CTRLA.ENABLE) Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 503: Register Summary

    8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-Synchronized" and/or "Write-Synchronized" property in each individual register description. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 504 Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 505 CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the Reset is complete. This bit is not Enable-Protected. Value Description There is no ongoing reset operation. The reset operation is ongoing. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 506 These bits define on which edge or level the NMI triggers. Value Name Description NONE No detection RISE Rising-edge detection FALL Falling-edge detection BOTH Both-edge detection HIGH High-level detection Low-level detection 0x6 - 0x7 - Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 507 This flag is set when the NMI pin matches the NMI sense configuration, and will generate an interrupt request. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the non-maskable interrupt flag. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 508 Write synchronization for CTRLA.ENABLE bit is ongoing. Bit 0 – SWRST: Software Reset Synchronization Busy Status Value Description Write synchronization for CTRLA.SWRST bit is complete. Write synchronization for CTRLA.SWRST bit is ongoing. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 509 Description Event from pin EXTINTx is disabled. Event from pin EXTINTx is enabled and will be generated when EXTINTx pin matches the external interrupt sensing configuration. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 510 Writing a '1' to this bit will clear the External Interrupt x Enable bit, which disables the external interrupt. Value Description The external interrupt x is disabled. The external interrupt x is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 511 Writing a '1' to this bit will set the External Interrupt x Enable bit, which enables the external interrupt. Value Description The external interrupt x is disabled. The external interrupt x is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 512 INTENCLR/SET.EXTINT[x] is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the External Interrupt x flag. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 513 ASYNCH[7:0] Access Reset Bits 15:0 – ASYNCH[15:0]: Asynchronous Edge Detection Mode Value Description The EXTINT edge detection is synchronously operated. The EXTINT edge detection is asynchronously operated. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 514 These bits define on which edge or level the interrupt or event for EXTINT[n*8+x] will be generated. Value Name Description NONE No detection RISE Rising-edge detection FALL Falling-edge detection BOTH Both-edge detection HIGH High-level detection Low-level detection 0x6 - 0x7 - Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 515: Nvmctrl - Non-Volatile Memory Controller

    Note:  A register with property "Enable-Protected" may contain bits that are not enable-protected. 28.3. Block Diagram Figure 28-1. Block Diagram NVMCTRL NVM Block Cache main array NVM Interface Command and Control RWWEE array Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 516: Signal Description

    Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write- Protection" property in each individual register description. Related Links PAC - Peripheral Access Controller on page 50 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 517: Functional Description

    In addition, a boot loader section can be allocated at the beginning of the main array, and an EEPROM section can be allocated at the end of the NVM main address space. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 518 The number of rows protected by BOOTPROT is given in Boot Loader Size, the number of rows allocated to the EEPROM are given in EEPROM Size. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 519 ADDR can be written by software, or the automatically loaded value from a write operation can be used. The new setting will stay in effect until the next Reset, or until the setting is changed again using Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 520 Alternatively, rows can be individually erased by the Erase Row command or the RWWEE Erase Row command to erase the NVM main address space or the RWWEE address space, respectively. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 521 (STATUS.LOCKE) will be set. Procedure for Erase Row • Write the address of the row to erase to ADDR. Any address within the row can be used. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 522 NVM main address space and is writable, regardless of the region lock status. Table 28-3. EEPROM Size EEPROM[2:0] Rows Allocated to EEPROM EEPROM Size in Bytes None 1024 2048 4096 8192 16384 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 523 The INVALL command can be issued using the Command bits in the Control A register to invalidate all cache lines (CTRLA.CMD=INVALL). Commands affecting NVM content automatically invalidate cache lines. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 524: Register Summary

    8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-Synchronized" and/or "Write-Synchronized" property in each individual register description. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 525 Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 526 Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. 0x05 0x06 0x07-0x0E - Reserved 0x0F Write Lockbits- write the LOCK register Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 527 Unlock Data Region - Unlocks the data region containing the address location in the ADDR register. When the Security Extension is enabled, only secure access can unlock secure regions. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 528 This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increased run time. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 529 15 wait states. This register is initialized to 0 wait states. Software can change this value based on the NVM access time and system frequency. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 530 64 bytes 128 bytes 256 bytes 512 bytes 1024 1024 bytes Bits 15:0 – NVMP[15:0]: NVM Pages Indicates the number of pages in the NVM main address space. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 531 Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the READY interrupt enable. This bit will read as the current value of the READY interrupt enable. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 532 Writing a '0' to this bit has no effect. Writing a '1' to this bit sets the READY interrupt enable. This bit will read as the current value of the READY interrupt enable. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 533 At least one error has occurred since the last clear. Bit 0 – READY: NVM Ready Value Description The NVM controller is busy programming or erasing. The NVM controller is ready to accept a new command. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 534 NVM load has been performed, this flag is set. It remains set until a page write or a page buffer clear (PBCLR) command is given. This bit can be cleared by writing a '1' to its bit location. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 535 (SPRM and CPRM) or when exiting sleep with SLEEPPRM set accordingly. Value Description NVM is not in power reduction mode. NVM is in power reduction mode. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 536 ADDR drives the hardware (16-bit) address to the NVM when a command is executed using CMDEX. This register is also automatically updated when writing to the page buffer. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 537 In order to set or clear these bits, the CMD register must be used. Default state after erase will be unlocked (0x0000). Value Description The corresponding lock region is locked. The corresponding lock region is not locked. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 538: Port - I/O Pin Controller

    Can be output to pin • Power saving using STANDBY mode – No access to configuration registers – Possible access to data registers (DIR, OUT or IN) Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 539: Block Diagram

    Each pin may be controlled by one or more peripheral multiplexer settings, which allow the pad to be routed internally to a dedicated peripheral function. When the setting is enabled, the selected peripheral Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 540 When the CPU is halted in debug mode, this peripheral will continue normal operation. If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper operation or Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 541 Since the IOBUS cannot wait for IN register resynchronization, the Control register (CTRL) must be configured to continuous sampling of all pins that need to be read via the IOBUS in order to prevent stale data from being read. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 542: Functional Description

    Port y PMUX[3:0] PAD y Pad y Line Bundle Periph Signal 0 Periph Signal 1 Peripheral Signals to be muxed to Pad y Periph Signal 15 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 543 CLK_PORT cycles. To remove the delay, the input synchronizers for each PORT group of eight pins can be configured to be always active, but this will increase power consumption. This Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 544 Input Input with pull-down Input with pull-up Output; input disabled Output; input enabled 29.6.3.2. Input Configuration Figure 29-4. I/O configuration - Standard Input PULLEN INEN PULLEN INEN Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 545 PULLEN INEN Figure 29-7. I/O Configuration - Totem-Pole Output with Enabled Input PULLEN INEN PULLEN INEN Figure 29-8. I/O Configuration - Output with Pull PULLEN INEN PULLEN INEN Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 546 Be careful when the event is output to pin. Due to the fact the events are received asynchronously, the I/O pin may have unpredictable levels, depending on the timing of when the events are received. When Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 547 The following priority is adopted: ® CPU IOBUS (No wait tolerated) EVSYS input events For input events that require different actions on the same I/O pin, refer to Events. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 548: Register Summary

    0x26 23:16 SAMPLING[23:16] 0x27 31:24 SAMPLING[31:24] 0x28 PINMASK[7:0] 0x29 15:8 PINMASK[15:8] WRCONFIG 0x2A 23:16 DRVSTR SLEWLIM ODRAIN PULLEN INEN PMUXEN 0x2B 31:24 HWSEL WRPINCFG WRPMUX PMUX[3:0] Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 549 INEN PMUXEN 0x58 PINCFG24 DRVSTR SLEWLIM ODRAIN PULLEN INEN PMUXEN 0x59 PINCFG25 DRVSTR SLEWLIM ODRAIN PULLEN INEN PMUXEN 0x5A PINCFG26 DRVSTR SLEWLIM ODRAIN PULLEN INEN PMUXEN Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 550: Register Description

    Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to Register Access Protection. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 551 The corresponding I/O pin in the PORT group is configured as an input. The corresponding I/O pin in the PORT group is configured as an output. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 552 Value Description The corresponding I/O pin in the PORT group will keep its configuration. The corresponding I/O pin in the PORT group is configured as input. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 553 Description The corresponding I/O pin in the PORT group will keep its configuration. The corresponding I/O pin in the PORT group is configured as an output. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 554 Writing '1' to a bit will toggle the corresponding bit in the DIR register, which reverses the direction of the I/O pin. Value Description The corresponding I/O pin in the PORT group will keep its configuration. The direction of the corresponding I/O pin is toggled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 555 The I/O pin output is driven low, or the input is connected to an internal pull-down. The I/O pin output is driven high, or the input is connected to an internal pull-up. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 556 The corresponding I/O pin in the PORT group will keep its configuration. The corresponding I/O pin output is driven low, or the input is connected to an internal pull- down. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 557 The corresponding I/O pin in the group will keep its configuration. The corresponding I/O pin output is driven high, or the input is connected to an internal pull- Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 558 Value Description The corresponding I/O pin in the PORT group will keep its configuration. The corresponding OUT bit value is toggled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 559 These bits are cleared when the corresponding I/O pin input sampler detects a logical low level on the input pin. These bits are set when the corresponding I/O pin input sampler detects a logical high level on the input pin. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 560 Value Description The I/O pin input synchronizer is disabled. The I/O pin input synchronizer is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 561 Writing '1' to this bit updates the configuration of the selected pins with the written WRCONFIG.DRVSTR, WRCONFIG.SLEWLIM, WRCONFIG.ODRAIN, WRCONFIG.PULLEN, WRCONFIG.INEN, WRCONFIG.PMUXEN and WRCONFIG.PINMASK values. This bit will always read as zero. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 562 Bit 17 – INEN: Input Enable This bit determines the new value written to PINCFGy.INEN for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 563 The configuration of the corresponding I/O pin in the half-word group will be left unchanged. The configuration of the corresponding I/O pin in the half-word PORT group will be updated. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 564 Table 29-4. PORT Event x Action ( x = [3..0] ) Value Name Description Output register of pin will be set to level of event. Set output register of pin on event. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 565 Event action to be executed on PIN 0. PIN1 Event action to be executed on PIN 1. 0x31 PIN31 Event action to be executed on PIN 31. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 566 Not all possible values for this selection may be valid. For more details, refer to the I/O Multiplexing and Considerations. PMUXE[3:0] Name Description Peripheral function A selected Peripheral function B selected Peripheral function C selected Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 567 Peripheral function D selected Peripheral function E selected Peripheral function F selected Peripheral function G selected Peripheral function H selected Peripheral function I selected 0x9-0xF Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 568 Writing a zero to this bit allows the PORT to control the pad direction via the Data Direction register (DIR) and output drive value via the Data Output Value register (OUT). The peripheral multiplexer value in Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 569 The peripheral multiplexer selection is disabled, and the PORT registers control the direction and output drive value. The peripheral multiplexer selection is enabled, and the selected peripheral function controls the direction and output drive value. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 570: Evsys - Event System

    Synchronized Path Channel_EVT_m SleepWalking Detector Channel_EVT_0 To Peripheral x PERIPHERAL0 Edge Detector Peripheral x EVT ACK Event Acknowledge PERIPHERAL n Resynchronized Path CHANNEL0.EDGSEL CHANNEL0.EVGEN SWEVT.CHANNEL0 GCLK_EVSYS_0 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 571: Signal Description

    When the CPU is halted in debug mode, this peripheral will continue normal operation. If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper operation or Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 572: Functional Description

    The user multiplexer defines the channel to be connected to which event user. Each user multiplexer is dedicated to one event user. A user multiplexer receives all event channels output and must be Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 573 When using the synchronous path, the channel is able to generate interrupts. The channel busy n bit in the Channel Status register (CHSTATUS.CHBUSYn) are also updated and available for use. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 574 The Event Detected Channel n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.EVDn) is set when an event coming from the event generator configured on channel n is detected. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 575 GCLK_EVSYS_CHANNEL_n clock (i.e., up to five GCLK_EVSYS_CHANNEL_n clock cycles). A channel will behave differently in different sleep modes regarding to CHANNELn.RUNSTDBY and CHANNELn.ONDEMAND, as shown in the table below: Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 576: Register Summary

    OVR1 OVR0 0x19 15:8 INTFLAG 0x1A 23:16 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0 0x1B 31:24 0x1C CHANNEL[7:0] 0x1D 15:8 SWEVT 0x1E 23:16 0x1F 31:24 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 577: Register Description

    Protection" property in each individual register description. Refer to Register Access Protection and PAC - Peripheral Access Controller. Related Links PAC - Peripheral Access Controller on page 50 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 578 Writing '1' to this bit resets all registers in the EVSYS to their initial state. Note:  Before applying a Software Reset it is recommended to disable the event generators. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 579 This bit is cleared when at least one of the event users connected to the channel is not ready. This bit is set when all event users connected to channel n are ready to handle incoming events on channel n. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 580 Writing '1' to this bit will clear the Overrun Channel n Interrupt Enable bit, which disables the Overrun Channel n interrupt. Value Description The Overrun Channel n interrupt is disabled. The Overrun Channel n interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 581 Writing '1' to this bit will set the Overrun Channel n Interrupt Enable bit, which disables the Overrun Channel n interrupt. Value Description The Overrun Channel n interrupt is disabled. The Overrun Channel n interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 582 When the event channel path is asynchronous, the OVRn interrupt flag will not be set. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Overrun Detected Channel n interrupt flag. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 583 Writing '0' to this bit has no effect. Writing '1' to this bit will trigger a software event for the channel n. These bits will always return zero when read. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 584 These bits set the type of edge detection to be used on the channel. These bits must be written to zero when using the asynchronous path. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 585 Period 2 0x0A RTC PER3 Period 3 0x0B RTC PER4 Period 4 0x0C RTC PER5 Period 5 0x0D RTC PER6 Period 6 0x0E RTC PER7 Period 7 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 586 TC0 OVF Overflow/Underflow 0x2B TC0 MCX0 Match/Capture 0 0x2C TC0 MCX1 Match/Capture 1 0x2D TC1 OVF Overflow/Underflow 0x2E TC1 MCX0 Match/Capture 0 0x2F TC1 MCX1 Match/Capture 1 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 587 CCL LUTOUT0 CCL output 0x43 CCL LUTOUT1 CCL output 0x44 CCL LUTOUT2 CCL output 0x45 CCL LUTOUT3 CCL output 0x46 PAC EVT Access Error 0x47-0x7F Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 588 Note that to select channel m, the value (m+1) must be written to the USER.CHANNEL bit group. Value Channel Number 0x00 No channel output selected 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09-0xFF Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 589 = 12 TCC0 MC1 Match/Capture 1 Asynchronous, synchronous, and resynchronized paths m = 13 TCC0 MC2 Match/Capture 2 Asynchronous, synchronous, and resynchronized paths Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 590 = 26 CCL LUTIN 2 CCL input Asynchronous, synchronous, and resynchronized paths m = 27 CCL LUTIN 3 CCL input Asynchronous, synchronous, and resynchronized paths Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 591 = 29 MTB START Tracing start Asynchronous, synchronous, and resynchronized paths m = 30 MTB STOP Tracing stop Asynchronous, synchronous, and resynchronized paths others Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 592: Sercom - Serial Communication Interface

    SERCOM SPI – SERCOM Serial Peripheral Interface on page 645 SERCOM I2C – SERCOM Inter-Integrated Circuit on page 678 SERCOM USART and I2C Configurations on page 30 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 593: Block Diagram

    The SERCOM can operate in any sleep mode where the selected clock source is running. SERCOM interrupts can be used to wake up the device from sleep modes. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 594 All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except the following registers: • Interrupt Flag Clear and Status register (INTFLAG) • Status register (STATUS) • Data register (DATA) Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 595: Functional Description

    The SERCOM must be configured to the desired mode by writing the Operating Mode bits in the Control A register (CTRLA.MODE). Refer to table SERCOM Modes for details. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 596 (divide-by-1) output is used while receiving. For synchronous communication, the /2 (divide-by-2) output is used. This functionality is automatically configured, depending on the selected operating mode. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 597 The BAUD register values that will affect the average frequency over a � single frame lead to an integer increase in the cycles per frame (CPF) ��� = � + � ��� � ���� where Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 598 Figure 31-4. Address With Mask ADDR Match ADDRMASK rx shift register Two Unique Addresses The two addresses written to ADDR and ADDRMASK will cause a match. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 599 The peripheral can operate in any sleep mode where the selected serial clock is running. This clock can be external or generated by the internal baud-rate generator. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 600 Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Required read-synchronization is denoted by the "Read-Synchronized" property in the register description. Related Links Register Synchronization on page 116 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 601: Sercom Usart - Sercom Universal Synchronous And Asynchronous Receiver And Transmitter

    ISO 7816 T=0 or T=1 protocols for Smart Card interfacing • RS485 Support • Start-of-frame detection • Can work with DMA Related Links SERCOM USART and I2C Configurations on page 30 Features on page 592 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 602: Block Diagram

    The combined configuration of PORT and the Transmit Data Pinout and Receive Data Pinout bit fields in the Control A register (CTRLA.TXPO and CTRLA.RXPO, respectively) will define the physical position of the USART signals in Table 32-2. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 603 32.5.8. Register Access Protection Registers with write-access can be write-protected optionally by the peripheral access controller (PAC). PAC Write-Protection is not available for the following registers: Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 604: Functional Description

    Parity bit. Either odd or even. Sp, [Sp] Stop bit. Signal is always high. IDLE No frame is transferred on the communication line. Signal is always high in this state. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 605 Writing ‘1’ to the Software Reset bit in the Control A register (CTRLA.SWRST) will reset all registers of this peripheral to their initial states, except the DBGCTRL register, and the peripheral is disabled. Refer to the CTRLA register description for details. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 606 XCK. When CTRLA.CPOL is '1', the data will be changed on the falling edge of XCK, and sampled on the rising edge of XCK. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 607 Interrupt Flag Status and Clear register (INTFLAG.RXC) will be set, and the optional interrupt will be generated. The received data can be read from the DATA register when the Receive Complete interrupt flag is set. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 608 (Data bits+Parity) 94.12 107.69 +5.88/-7.69 ±2.5 94.92 106.67 +5.08/-6.67 ±2.0 95.52 105.88 +4.48/-5.88 ±2.0 96.00 105.26 +4.00/-5.26 ±2.0 96.39 104.76 +3.61/-4.76 ±1.5 96.70 104.35 +3.30/-4.35 ±1.5 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 609 32.6.3.1. Parity Even or odd parity can be selected for error checking by writing 0x1 to the Frame Format bit field in the Control A register (CTRLA.FORM). Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 610 Transmission and reception can be encoded IrDA compliant up to 115.2 kb/s. IrDA modulation and demodulation work in the following configuration: • IrDA encoding enabled (CTRLB.ENC=1), • Asynchronous mode (CTRLA.CMODE=0), Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 611 If the received Sync character is not 0x55, then the Inconsistent Sync Field error flag (STATUS.ISF) is set along with the Error interrupt flag (INTFLAG.ERROR), and the baud rate is unchanged. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 612 Inverse transmission and reception (CTRLA.RXINV=1 and CTRLA.TXINV=1) • Single bidirectional data line (CTRLA.TXPO and CTRLA.RXPO configured to use the same data pin) • Even parity (CTRLB.PMODE=0) Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 613 1 bit time. Figure 32-17. T=0 Protocol with Parity Error Error Start Guard Guard Start Time1 Time2 Repetition Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 614 While the transmitter is idle (no transmission in progress), characters can be received on RxD without triggering a collision. Figure 32-18. Collision Checking 8-bit character, single stop bit Collision checked Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 615 8MHz Internal Oscillator and USART clock active while the frame is being received. In this case, the CPU will not wake up until the Receive Complete interrupt is generated. Related Links Electrical Characteristics on page 1147 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 616 An interrupt request is generated when the interrupt flag is set and if the corresponding interrupt is enabled. The interrupt request remains active until either the interrupt flag is cleared, the interrupt is Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 617 Transmitter Enable bit in the Control B register (CTRLB.TXEN) Note:  CTRLB.RXEN is write-synchronized somewhat differently. See also CTRLB for details. Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 618: Register Summary

    SWRST 0x1D 15:8 SYNCBUSY 0x1E 23:16 0x1F 31:24 0x20 RXERRCNT RXERRCNT[7:0] 0x21 Reserved 0x27 0x28 DATA[7:0] DATA 0x29 15:8 DATA[8:8] 0x2A Reserved 0x2F 0x30 DBGCTRL DBGSTOP Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 619: Register Description

    Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 620 Falling XCK edge Falling XCK edge Rising XCK edge Bit 28 – CMODE: Communication Mode This bit selects asynchronous or synchronous communication. This bit is not synchronized. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 621 SERCOM PAD[2] is used for data reception PAD[3] SERCOM PAD[3] is used for data reception Bits 17:16 – TXPO[1:0]: Transmit Data Pinout These bits define the transmit data (TxD) and XCK pin configurations. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 622 TxD is inverted. Bit 8 – IBON: Immediate Buffer Overflow Notification This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is asserted when a buffer overflow occurs. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 623 Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. This bit is not enable-protected. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 624 Value Description There is no reset operation ongoing. The reset operation is ongoing. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 625 USART is enabled, CTRLB.TXEN will be cleared, and SYNCBUSY.CTRLB will be set and remain set until the transmitter is enabled. When the transmitter is enabled, CTRLB.TXEN will read back as '1'. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 626 Start-of-frame detection enabled. Both RXC and RXS wake up the device from all sleep modes. Bit 8 – COLDEN: Collision Detection Enable This bit enables collision detection. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 627 These bits select the number of bits in a character. These bits are not synchronized. CHSIZE[2:0] Description 8 bits 9 bits 0x2-0x4 Reserved 5 bits 6 bits 7 bits Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 628 This bit controls how many times NACK will be sent on parity error reception. This bit is only valid in ISO7816 T=0 mode and when CTRLC.INACK=0. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 629 Value Description The receiver is disabled or being enabled. The receiver is enabled or will be enabled when the USART is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 630 Rate Generator section. • Bits 12:0 - BAUD[21:0]: Baud Value These bits control the clock generation, as described in the SERCOM Clock Generation – Baud- Rate Generator section. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 631 IrDA receiver with regards to the serial engine clock ��� ����� ≥ RXPL + 2 ⋅ �� ��� Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 632 Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Receive Start Interrupt Enable bit, which disables the Receive Start interrupt. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 633 Writing '1' to this bit will clear the Data Register Empty Interrupt Enable bit, which disables the Data Register Empty interrupt. Value Description Data Register Empty interrupt is disabled. Data Register Empty interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 634 Writing '0' to this bit has no effect. Writing '1' to this bit will set the Receive Start Interrupt Enable bit, which enables the Receive Start interrupt. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 635 Writing '1' to this bit will set the Data Register Empty Interrupt Enable bit, which enables the Data Register Empty interrupt. Value Description Data Register Empty interrupt is disabled. Data Register Empty interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 636 This flag is set when there are unread data in DATA. Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 637 This flag is set when DATA is empty and ready to be written. Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 638 Reading this bit before reading the Data register will indicate the error status of the next character to be read. This bit is cleared by writing '1' to the bit or by disabling the receiver. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 639 This bit is set if parity checking is enabled (CTRLA.FORM is 0x1, 0x5, or 0x7) and a parity error is detected. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 640 Bit 1 – ENABLE: SERCOM Enable Synchronization Busy Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the SYNCBUSY.ENABLE bit will be set until synchronization is complete. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 641 Writes to any register while synchronization is on-going will be discarded and an APB error will be generated. Value Description SWRST synchronization is not busy. SWRST synchronization is busy. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 642 Bits 7:0 – RXERRCNT[7:0]: Receive Error Count This register records the total number of parity errors and NACK errors combined in ISO7816 mode (CTRLA.FORM=0x7). This register is automatically cleared on read. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 643 Writing these bits will write the Transmit Data register. This register should be written only when the Data Register Empty Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 644 The baud-rate generator continues normal operation when the CPU is halted by an external debugger. The baud-rate generator is halted when the CPU is halted by an external debugger. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 645: Sercom Spi - Sercom Serial Peripheral Interface

    Wake on SS transition For t and t values, refer to SPI Timing Characteristics. SSCK Related Links SERCOM – Serial Communication Interface on page 592 Features on page 592 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 646: Block Diagram

    The combined configuration of PORT, the Data In Pinout and the Data Out Pinout bit groups in the Control A register (CTRLA.DIPO and CTRLA.DOPO) define the physical position of the SPI signals in the table above. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 647 33.5.8. Register Access Protection Registers with write-access can be write-protected optionally by the peripheral access controller (PAC). PAC Write-Protection is not available for the following registers: Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 648: Functional Description

    To signal the end of a transaction, the master will pull the SS line high 33.6.2. Basic Operation 33.6.2.1. Initialization The following registers are enable-protected, meaning that they can only be written when the SPI is disabled (CTRL.ENABLE=0): Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 649 This clock is used to directly clock the SPI shift register. Related Links Clock Generation – Baud-Rate Generator on page 596 Asynchronous Arithmetic Mode BAUD Value Selection on page 597 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 650 Falling, setup Rising, sample Note:  Leading edge is the first clock edge in a clock cycle. Trailing edge is the second clock edge in a clock cycle. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 651 If the receiver is enabled (CTRLA.RXEN=1), the contents of the shift register will be transferred to the two-level receive buffer. The transfer takes place in the same clock cycle as the last Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 652 When the SPI is configured for slave operation (CTRLA.MODE=0x2) with address recognition (CTRLA.FORM is 0x2), the SERCOM address recognition logic is enabled: the first character in a transaction is checked for an address match. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 653 SPI master can use general purpose I/O pins to control the SS line to each of the slaves on the bus, as shown in Multiple Slaves in Parallel. In this configuration, the single selected SPI slave will drive the tri-state MISO line. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 654 If back-to-back frames are transmitted, the SS pin will always be driven high for a minimum of one baud cycle between frames. Hardware Controlled SS, the time T is between one and two baud cycles depending on the SPI transfer mode. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 655 Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) will be set when the interrupt condition is met. Each interrupt can be individually Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 656 Receiver Enable bit in the CTRLB register (CTRLB.RXEN) Note:  CTRLB.RXEN is write-synchronized somewhat differently. See also CTRLB for details. Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 657: Register Summary

    31:24 0x20 Reserved 0x23 0x24 ADDR[7:0] 0x25 15:8 ADDR 0x26 23:16 ADDRMASK[7:0] 0x27 31:24 0x28 DATA[7:0] DATA 0x29 15:8 DATA[8:8] 0x2A Reserved 0x2F 0x30 DBGCTRL DBGSTOP Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 658: Register Description

    Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write- Protection" property in each individual register description. Refer to Register Access Protection. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 659 SCK is high when idle. The leading edge of a clock cycle is a falling edge, while the trailing edge is a rising edge. Bit 28 – CPHA: Clock Phase In combination with the Clock Polarity bit (CPOL), this bit determines the SPI transfer mode. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 660 (SS) is controlled by DOPO, while in master operation the SS line is controlled by the port configuration. In master operation, DO is MOSI. In slave operation, DO is MISO. These bits are not synchronized. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 661 This bit is not enable-protected. Value Description The peripheral is disabled or being disabled. The peripheral is enabled or being enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 662 CTRLA.SWRST and SYNCBUSY. SWRST will both be cleared when the reset is complete. This bit is not enable-protected. Value Description There is no reset operation ongoing. The reset operation is ongoing. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 663 Bits 15:14 – AMODE[1:0]: Address Mode These bits set the slave addressing mode when the frame format (CTRLA.FORM) with address is used. They are unused in master mode. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 664 SS line is high when DATA is written, it will be transferred immediately to the shift register. Bits 2:0 – CHSIZE[2:0]: Character Size CHSIZE[2:0] Name Description 8BIT 8 bits 9BIT 9 bits 0x2-0x7 Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 665 PAC Write-Protection, Enable-Protected   BAUD[7:0] Access Reset Bits 7:0 – BAUD[7:0]: Baud Register These bits control the clock generation, as described in the SERCOM Clock Generation – Baud-Rate Generator. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 666 Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Transmit Complete Interrupt Enable bit, which disable the Transmit Complete interrupt. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 667 Writing '1' to this bit will clear the Data Register Empty Interrupt Enable bit, which disables the Data Register Empty interrupt. Value Description Data Register Empty interrupt is disabled. Data Register Empty interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 668 Writing '0' to this bit has no effect. Writing '1' to this bit will set the Transmit Complete Interrupt Enable bit, which enables the Transmit Complete interrupt. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 669 Writing '1' to this bit will set the Data Register Empty Interrupt Enable bit, which enables the Data Register Empty interrupt. Value Description Data Register Empty interrupt is disabled. Data Register Empty interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 670 Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 0 – DRE: Data Register Empty This flag is cleared by writing new data to DATA. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 671 This flag is set when DATA is empty and ready for new data to transmit. Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 672 Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. Value Description No Buffer Overflow has occurred. A Buffer Overflow has occurred. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 673 Writes to any register (except for CTRLA.SWRST) while enable synchronization is on-going will be discarded and an APB error will be generated. Value Description Enable synchronization is not busy. Enable synchronization is busy. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 674 Writes to any register while synchronization is on-going will be discarded and an APB error will be generated. Value Description SWRST synchronization is not busy. SWRST synchronization is busy. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 675 These bits hold the address mask when the transaction format with address is used (CTRLA.FORM, CTRLB.AMODE). Bits 7:0 – ADDR[7:0]: Address These bits hold the address when the transaction format with address is used (CTRLA.FORM, CTRLB.AMODE). Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 676 Writing these bits will write the transmit data buffer. This register should be written only when the Data Register Empty Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 677 The baud-rate generator continues normal operation when the CPU is halted by an external debugger. The baud-rate generator is halted when the CPU is halted by an external debugger. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 678: Sercom I C - Sercom Inter-Integrated Circuit

    • Address range • Two unique addresses can be used with DMA Related Links SERCOM USART and I2C Configurations on page 30 Features on page 592 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 679: Block Diagram

    This peripheral can continue to operate in any sleep mode where its source clock is running. The interrupts can wake up the device from sleep modes. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 680 Registers with write-access can be write-protected optionally by the peripheral access controller (PAC). PAC Write-Protection is not available for the following registers: • Interrupt Flag Clear and Status register (INTFLAG) Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 681: Functional Description

    Figure 34-2. Basic I C Transaction Diagram 6..0 7..0 7..0 ADDRESS DATA DATA ACK/NACK ADDRESS DATA DATA Direction Address Packet Data Packet #0 Data Packet #1 Transaction Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 682 Select the inactive bus time-out in the Inactive Time-Out bit group in the CTRLA register (CTRLA.INACTOUT). 5.2. Write the Baud Rate register (BAUD) to generate the desired baud rate. In Slave mode: Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 683 When the bus is IDLE it is ready for a new transaction. If a start condition is issued on the bus by another C master in a multi-master setup, the bus becomes BUSY (0b11). The bus will re-enter IDLE either Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 684 "Mn" (M1, M2..) indicate the nodes the bus logic can jump to, based on software or hardware interaction. This diagram is used as reference for the description of the I C master operation throughout the document. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 685 Behavioral Diagram (SCLSM=1). This strategy can be used when it is not necessary to check DATA before acknowledging. Note:  I C High-speed (Hs) mode requires CTRLA.SCLSM=1. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 686 T . Likewise, T will be in a state between T and T FALL RISE HIGH until a high state has been detected. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 687 C standard Fm+ (Fast-mode plus) requires a nominal high to low SCL ratio of 1:2, and BAUD should be set accordingly. At a minimum, BAUD.BAUD and/or BAUD.BAUDLOW must be non- zero. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 688 C slave is busy with other tasks or sleeping. Therefore, it is not able to respond. In this event, the next step can be either issuing a stop condition (recommended) Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 689 In this case, a lost arbitration will prevent setting INTFLAG.SB. Instead, INTFLAG.MB will indicate a change in arbitration. Handling of lost arbitration is the same as for data bit transmission. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 690 This implies the following procedure for a 10-bit read operation: Write the 10-bit address to ADDR.ADDR[10:1]. ADDR.TENBITEN must be '1', the direction bit (ADDR.ADDR[0]) must be '0' (can be written simultaneously with ADDR). Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 691 Note:  For I C High-speed mode (Hs), SCLSM=1 is required. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 692 Typically, software will immediately acknowledge the address packet by sending an ACK/NACK bit. The C slave Command bit field in the Control B register (CTRLB.CMD) can be written to '0x3' for both read Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 693 C slave must expect a stop or a repeated start to be received. The I C slave must release the data line to allow the I C master to generate a stop or repeated Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 694 Eventually, at the end of the group command, a single STOP is generated by the master. At this point a STOP interrupt is asserted. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 695 In this mode, the internal I C tri-state drivers are bypassed, and an external I C compliant tri- state driver is needed when connecting to an I C bus. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 696 Data received (RX) (Slave receive mode) (request cleared when data is read) Data Ready (DRDY) Address Match (AMATCH) Stop received (PREC) Error (ERROR) Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 697 34.6.4.2. Interrupts The I C slave has the following interrupt sources. These are asynchronous interrupts. They can wake-up the device from any sleep mode: • Error (ERROR) Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 698 Write to Bus State bits in the Status register (STATUS.BUSSTATE) • Address bits in the Address register (ADDR.ADDR) when in master operation. The following registers are synchronized when written: Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 699 • Data (DATA) when in master operation Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 700: Register Summary - I2C Slave

    Some registers are synchronized when read and/or written. Synchronization is denoted by the "Write- Synchronized" or the "Read-Synchronized" property in each individual register description. For details, refer to Synchronization. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 701 Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 702 Figure 34-9 SCL stretch only after ACK bit according to Figure 34-10 Bits 25:24 – SPEED[1:0]: Transfer Speed These bits define bus speed. These bits are not synchronized. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 703 This bit defines the functionality in standby sleep mode. This bit is not synchronized. Value Description Disabled – All reception is dropped. Wake on address match, if enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 704 CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. This bit is not enable-protected. Value Description There is no reset operation ongoing. The reset operation is ongoing. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 705 The operation is dependent on the slave interrupt flags, INTFLAG.DRDY and INTFLAG.AMATCH, in addition to STATUS.DIR. All interrupt flags (INTFLAG.DRDY, INTFLAG.AMATCH and INTFLAG.PREC) are automatically cleared when a command is given. This bit is not enable-protected. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 706 This bit enables PMBus group command support. When enabled, the Stop Recived interrupt flag (INTFLAG.PREC) will be set when a STOP condition is detected if the slave has been addressed since the last STOP condition on the bus. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 707 When smart mode is enabled, data is acknowledged automatically when DATA.DATA is read. This bit is not write-synchronized. Value Description Smart mode is disabled. Smart mode is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 708 Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Stop Received Interrupt Enable bit, which disables the Stop Received interrupt. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 709 Value Description The Stop Received interrupt is disabled. The Stop Received interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 710 Writing '0' to this bit has no effect. Writing '1' to this bit will set the Stop Received Interrupt Enable bit, which enables the Stop Received interrupt. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 711 Value Description The Stop Received interrupt is disabled. The Stop Received interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 712 This flag is cleared by hardware after a command is issued on the next address match. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Stop Received interrupt flag. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 713 The slave Clock Hold bit (STATUS.CLKHOLD) is set when the slave is holding the SCL line low, stretching the I2C clock. Software should consider this bit a read-only status flag that is set when INTFLAG.DRDY or INTFLAG.AMATCH is set. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 714 This bit is cleared automatically if responding to an address match with an ACK or a NACK (writing 0x3 to CTRLB.CMD), or INTFLAG.AMATCH is cleared. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 715 Writing a '1' to this bit will clear the status. Writing a '0' to this bit has no effect. Value Description No bus error detected. Bus error detected. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 716 Writes to any register while synchronization is on-going will be discarded and an APB error will be generated. Value Description SWRST synchronization is not busy. SWRST synchronization is busy. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 717 Bit 0 – GENCEN: General Call Address Enable A general call address is an address consisting of all-zeroes, including the direction bit (master write). Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 718 Value Description General call address recognition disabled. General call address recognition enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 719 C bus operations. The operation performed depends on the state of CTRLB.ACKACT, CTRLB.SMEN and the type of access (read/write). Writing or reading DATA.DATA when not in smart mode does not require synchronization. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 720: Register Summary - I2C Master

    SYNCBUSY 0x1E 23:16 0x1F 31:24 0x21 Reserved 0x23 0x24 0x25 15:8 TENBITEN LENEN ADDR[2:0] ADDR 0x26 23:16 LEN[7:0] 0x27 31:24 0x28 Reserved 0x2F 0x30 DBGCTRL DBGSTOP Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 721: Register Description - I C Master

    Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 722 Enabling this option is necessary for SMBus compatibility, but can also be used in a non-SMBus set-up. Calculated time-out periods are based on a 100kHz baud rate. These bits are not synchronized. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 723 SB or MB will be set as normal, but CLKHOLD will be released. The MEXTTOUT and BUSERR status bits will be set. This bit is not synchronized. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 724 The value written to CTRL.ENABLE will read back immediately and the Synchronization Enable Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. This bit is not enable-protected. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 725 CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. This bit is not enable-protected. Value Description There is no reset operation ongoing. The reset operation is ongoing. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 726 Commands can only be issued when either the Slave on Bus interrupt flag (INTFLAG.SB) or Master on Bus interrupt flag (INTFLAG.MB) is '1'. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 727 When smart mode is enabled, acknowledge action is sent when DATA.DATA is read. This bit is not write-synchronized. Value Description Smart mode is disabled. Smart mode is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 728 This bit field is used to derive the SCL high time if BAUD.BAUDLOW is non-zero. If BAUD.BAUDLOW is zero, BAUD will be used to generate both high and low periods of the SCL. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 729 For more information on how to calculate the frequency, see SERCOM Clock Generation – Baud-Rate Generator. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 730 Writing '1' to this bit will clear the Master on Bus Interrupt Enable bit, which disables the Master on Bus interrupt. Value Description The Master on Bus interrupt is disabled. The Master on Bus interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 731 Writing '1' to this bit will set the Master on Bus Interrupt Enable bit, which enables the Master on Bus interrupt. Value Description The Master on Bus interrupt is disabled. The Master on Bus interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 732 Writing '1' to this bit location will clear the MB flag. The transaction will not continue or be terminated until one of the above actions is performed. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 733 Writing '0' to this bit has no effect. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 734 INTFLAG.SB or INTFLAG.MB is set. This bit is cleared when the corresponding interrupt flag is cleared and the next operation is given. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 735 Writing the ADDR.ADDR register will automatically clear STATUS.ARBLOST. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. This bit is not write-synchronized. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 736 Writing the ADDR.ADDR register will automatically clear the BUSERR flag. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. This bit is not write-synchronized. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 737 Enable synchronization is busy. Bit 0 – SWRST: Software Reset Synchronization Busy Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit will be set until synchronization is complete. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 738 Writes to any register while synchronization is on-going will be discarded and an APB error will be generated. Value Description SWRST synchronization is not busy. SWRST synchronization is busy. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 739 This bit enables High-speed mode for the current transfer from repeated START to STOP. This bit can be written simultaneously with ADDR for a high speed transfer. Value Description High-speed transfer disabled. High-speed transfer enabled. Bit 13 – LENEN: Transfer Length Enable Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 740 The I C master control logic uses bit 0 of ADDR as the bus protocol’s read/write flag (R/W); 0 for write and 1 for read. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 741 C bus operations. The operation performed depends on the state of CTRLB.ACKACT, CTRLB.SMEN and the type of access (read/write). Writing or reading DATA.DATA when not in smart mode does not require synchronization. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 742 The baud-rate generator continues normal operation when the CPU is halted by an external debugger. The baud-rate generator is halted when the CPU is halted by an external debugger. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 743: Tc - Timer/Counter

    Pulse-width capture – Time-stamp capture • One input event • Interrupts/output events on: – Counter overflow/underflow – Compare match or capture • Internal prescaler • DMA support Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 744: Block Diagram

    Capture input Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be mapped on several pins. Related Links Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 745: Product Dependencies

    Interrupt Controller (NVIC) must be configured first. Refer to Nested Vector Interrupt Controller for details. Related Links Nested Vector Interrupt Controller on page 44 35.5.6. Events The events of this peripheral are connected to the Event System. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 746: Functional Description

    The clock control is handled externally (e.g. counting external events) For compare operations, the CC are referred to as “compare channels” For capture operations, the CC are referred to as “capture channels.” Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 747 (CTRLA.PRESCALER). – If the prescaler is used, select a prescaler synchronization operation via the Prescaler and Counter Synchronization bit group in the Control A register (CTRLA.PRESYNC). Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 748 TC2 respectively). The odd-numbered partner (TC1 or TC3 respectively) will act as slave, and the Slave bit in the Status register (STATUS.SLAVE) will be set. The register values of a slave will Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 749 (ZERO or TOP, depending on direction set by CTRLBSET.DIR or CTRLBCLR.DIR). All waveforms are cleared and the Stop bit in the Status register is set (STATUS.STOP). Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 750 CLK_TC_CNT (see Normal Frequency Operation). An interrupt/and or event can be generated on comparison match if enabled. The same condition generates a DMA request. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 751 When up-counting, the WO[x] is set at start or compare match between the COUNT and TOP values, and cleared on compare match between COUNT and CCx Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 752 As long as the respective buffer valid status flag (PERBUFV or CCBUFVx) are set to '1', related syncbusy bits are set (SYNCBUSY.PER or SYNCBUSY.CCx), a write to the respective PER/PERBUF or Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 753 The counter period can be changed by writing a new TOP value to the Period register (PER or CC0, depending on the waveform generation mode), any period update on registers (PER or CCx) is effective after the synchronization delay, whatever double buffering enabling is. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 754 The period register is always updated on the update condition, as shown in Figure 35-10. This prevents wraparound and the generation of odd waveforms. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 755 (IF) and generate the optional interrupt, event or DMA request. CCBUFx register value can't be read, all captured data must be read from CCx register. Figure 35-11. Capture Double Buffering "capture" COUNT CCBx "INT/DMA request" data read Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 756 � = � � dutyCycle = � � Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 757 To enable the operation on opposite edges, the input signal to capture must be inverted (refer to DRVCTRL.INVEN or EVCTRL.TCEINV). Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 758 The timer/counter can detect capture overflow of the input capture channels: When a new capture event is detected while the Capture Channel interrupt flag (INTFLAG.MCx) is still set, the new time-stamp will not be stored and INTFLAG.ERR will be set. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 759 Nested Vector Interrupt Controller on page 44 35.6.6. Events The TC can generate the following output events: • Overflow/Underflow (OVF) • Match or Capture Channel x (MCx) Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 760 • Count Value register (COUNT): synchronization is done on demand through READSYNC command (CTRLBSET.CMD). Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 761: Register Summary

    0x1B PER[7:0] 0x1C CC[7:0] 0x1D CC[7:0] 0x1E Reserved 0x1F Reserved 0x20 Reserved 0x21 Reserved 0x22 Reserved 0x23 Reserved 0x24 Reserved 0x25 Reserved 0x26 Reserved 0x27 Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 762 COUNT 0x15 15:8 COUNT[15:8] 0x16 Reserved 0x17 Reserved 0x18 Reserved 0x19 Reserved 0x1A Reserved 0x1B Reserved 0x1C CC[7:0] 0x1D 15:8 CC[15:8] 0x1E CC[7:0] 0x1F 15:8 CC[5:8] Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 763 STOP 0x0C WAVE WAVEGEN[1:0] 0x0D DRVCTRL INVEN1 INVEN0 0x0E Reserved 0x0F DBGCTRL DBGRUN 0x10 COUNT STATUS CTRLB ENABLE SWRST 0x11 15:8 SYNCBUSY 0x12 23:16 0x13 31:24 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 764 0x35 15:8 CCBUF[15:8] CCBUF1 0x36 23:16 CCBUF[23:16] 0x37 31:24 CCBUF[31:24] 0x38 Reserved 0x39 Reserved 0x3A Reserved 0x3B Reserved 0x3C Reserved 0x3D Reserved 0x3E Reserved 0x3F Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 765: Register Description

    Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 766 These bits select the counter prescaler factor. These bits are not synchronized. Value Name Description DIV1 Prescaler: GCLK_TC DIV2 Prescaler: GCLK_TC/2 DIV4 Prescaler: GCLK_TC/4 DIV8 Prescaler: GCLK_TC/8 DIV16 Prescaler: GCLK_TC/16 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 767 Bits 3:2 – MODE[1:0]: Timer Counter Mode These bits select the counter mode. These bits are not synchronized. Value Name Description COUNT16 Counter in 16-bit mode COUNT8 Counter in 8-bit mode Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 768 These bits are used to select whether channel x is a capture or a compare channel. These bits are not synchronized. Value Description CAPTENx disables capture on channel x. CAPTENx enables capture on channel x. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 769 The CCBUFx and PERBUF buffer registers value are copied into CCx and PER registers on hardware update condition. The CCBUFx and PERBUF buffer registers value are not copied into CCx and PER registers on hardware update condition. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 770 Writing a '1' to this bit will clear the bit and make the counter count up. Value Description The timer/counter is counting up (incrementing). The timer/counter is counting down (decrementing). Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 771 After all the buffer registers are loaded correctly, the buffered registers can be unlocked. Writing a '0' to this bit has no effect. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 772 Writing a '1' to this bit will clear the bit and make the counter count up. Value Description The timer/counter is counting up (incrementing). The timer/counter is counting down (decrementing). Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 773 These bits define the event action the TC will perform on an event. Value Name Description Event action disabled RETRIGGER Start, restart or retrigger TC on event COUNT Count on event Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 774 Match/Capture event on channel x is disabled and will not be generated. Match/Capture event on channel x is enabled and will be generated for every compare/ capture. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 775 Match or Capture Channel x interrupt. Value Description The Match or Capture Channel x interrupt is disabled. The Match or Capture Channel x interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 776 Match or Capture Channel x interrupt. Value Description The Match or Capture Channel x interrupt is disabled. The Match or Capture Channel x interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 777 Writing a '1' to one of these bits will clear the corresponding Match or Capture Channel x interrupt flag In capture operation, this flag is automatically cleared when CCx register is read. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 778 For a capture channel x, the bit x is set when a valid capture value is stored in the CCBUFx register. The bit x is cleared automatically when the CCx register is read. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 779 1) This depends on the TC mode: In 8-bit mode, the top value is the Period Value register (PER). In 16- and 32-bit mode it is the respective MAX value. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 780 These bits are used to select inversion of the output or capture trigger input of channel x. Value Description Disable inversion of the WO[x] output and IO input pin. Enable inversion of the WO[x] output and IO input pin. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 781 Description The TC is halted when the device is halted in debug mode. The TC continues normal operation when the device is halted in debug mode. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 782 This bit is set when the synchronization of CTRLB between clock domains is started. Bit 1 – ENABLE: ENABLE Synchronization Busy This bit is cleared when the synchronization of ENABLE bit between the clock domains is complete. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 783 This bit is also set when the CCBUFx is written, and cleared on update condition. The bit is automatically cleared when the STATUS.CCBUFx bit is cleared. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 784 COUNT Offset:  0x14 Reset:  0x00 Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized   COUNT[7:0] Access Reset Bits 7:0 – COUNT[7:0]: Counter Value These bits contain the current counter value. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 785 Reset:  0x00 Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized   COUNT[15:8] Access Reset COUNT[7:0] Access Reset Bits 15:0 – COUNT[15:0]: Counter Value These bits contain the current counter value. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 786 PAC Write-Protection, Write-Synchronized, Read-Synchronized   COUNT[31:24] Access Reset COUNT[23:16] Access Reset COUNT[15:8] Access Reset COUNT[7:0] Access Reset Bits 31:0 – COUNT[31:0]: Counter Value These bits contain the current counter value. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 787 Bits 7:0 – PER[7:0]: Period Value These bits hold the value of the Period Buffer register PERBUF. The value is copied to PER register on UPDATE condition. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 788 These bits contain the compare/capture value in 8-bit TC mode. In Match frequency (MFRQ) or Match PWM (MPWM) waveform operation (WAVE.WAVEGEN), the CC0 register is used as a period register. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 789 These bits contain the compare/capture value in 16-bit TC mode. In Match frequency (MFRQ) or Match PWM (MPWM) waveform operation (WAVE.WAVEGEN), the CC0 register is used as a period register. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 790 These bits contain the compare/capture value in 32-bit TC mode. In Match frequency (MFRQ) or Match PWM (MPWM) waveform operation (WAVE.WAVEGEN), the CC0 register is used as a period register. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 791 Bits 7:0 – PERBUF[7:0]: Period Buffer Value These bits hold the value of the period buffer register. The value is copied to PER register on UPDATE condition. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 792 (CTRLBCLR.LUPD=1), the data from buffer registers will be copied into the corresponding CCx register under UPDATE condition (CTRLBSET.CMD=0x3), including the software update command. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 793 (CTRLBCLR.LUPD=1), the data from buffer registers will be copied into the corresponding CCx register under UPDATE condition (CTRLBSET.CMD=0x3), including the software update command. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 794 (CTRLBCLR.LUPD=1), the data from buffer registers will be copied into the corresponding CCx register under UPDATE condition (CTRLBSET.CMD=0x3), including the software update command. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 795: Tcc - Timer/Counter For Control Applications

    Two input events for counter – One input event for each channel • Output events: – Three output events (Count, Re-Trigger and Overflow) available for counter Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 796: Block Diagram

    Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be mapped on several pins. Related Links I/O Multiplexing and Considerations on page 27 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 797: Product Dependencies

    Nested Vector Interrupt Controller on page 44 36.5.6. Events The events of this peripheral are connected to the Event System. Related Links EVSYS – Event System on page 570 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 798: Functional Description

    The clock control is handled externally (e.g. counting external events). For compare operations, the CC are referred to as "compare channels." For capture operations, the CC are referred to as "capture channels." Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 799 For further details on how to configure asynchronous events routing, refer to section EVSYS – Event System. Related Links EVSYS – Event System on page 570 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 800 Prescaler outputs from 1 to 1/1024 are available. For a complete list of available prescaler outputs, see the register description for the Prescaler bit group in the Control A register (CTRLA.PRESCALER). Note:  When counting events, the prescaler is bypassed. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 801 When a stop is detected while the counter is running, the counter will maintain its current value. If the waveform generation (WG) is used, all waveforms are set to a state defined in Non-Recoverable State x Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 802 When received, the event level overrides the Direction settings (CTRLBSET.DIR or CTRLBCLR.DIR) and the direction bit value is updated accordingly. Increment Event Action Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 803 Waveform register (WAVE.WAVEGEN). This will influence how the waveform is generated and impose restrictions on the top value. The configurations are: • Normal Frequency (NFRQ) • Match Frequency (MFRQ) Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 804 (WO[x]) is toggled on each compare match between COUNT and CCx, and the corresponding Match or Capture Channel x Interrupt Flag (EVCTRL.MCEOx) will be set. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 805 Figure 36-6. Single-Slope PWM Operation CCx=ZERO CCx=TOP "clear" update "match" COUNT ZERO WO[x] The following equation calculates the exact resolution for a single-slope PWM (R ) waveform: PWM_SS Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 806 2� ⋅ TOP − CCx clock frequency (f ), and can be calculated by the following equation: � GCLK_TCC � PWM_DS GCLK_TCC N represents the prescaler divider used. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 807 Timer/counter matches CC Timer/counter matches CC when counting down when counting up In Normal and Match Frequency, the WAVE.POLx value represents the initial state of the waveform output. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 808 The counter period can be changed by writing a new Top value to the Period register (PER or CC0, depending on the waveform generation mode), any period update on registers (PER or CCx) is effective after the synchronization delay, whatever double buffering enabling is. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 809 The period register is always updated on the update condition, as shown in Figure 36-13. This prevents wraparound and the generation of odd waveforms. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 810 (IF) and generate the optional interrupt, event or DMA request. CCBUFx register value can't be read, all captured data must be read from CCx register. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 811 If EVCTRL.TCEINVx=1, the wraparound will happen on the falling edge. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 812 CCBUF0 CIRCC0EN UPDATE COUNT "ma tch" 36.6.3.3. Dithering Operation The TCC supports dithering on Pulse-width or Period on a 16, 32 or 64 PWM cycles frame. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 813 Writing DITHERCY in CCx will lead to an average PWM pulse width configured by the following formula. DITHERCY DITH4 mode: ������������ℎ = + CCx � GCLK_TCC Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 814 "match" Retrigger TOP(B) TOP(B) TOP(A) CIPEREN = 1 FaultA COUNT ZERO WO[0] POL0 = 1 WO[1] Keep on FaultB POL1 = 1 FaultA input FaultB input Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 815 Blanking can be enabled by writing an edge triggering configuration to the Fault n Blanking Mode bits in the Recoverable Fault n Configuration register Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 816 Fault B Input Qual x x x x x x x x x x x x x x x x x x x Fault Input B Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 817 36-25. Fault A and Fault B are qualified only during the cycle A and cycle B respectively: Fault A is disabled during cycle B, and Fault B is disabled during cycle A. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 818 LOCMAX - notifies by event or interrupt when a local maximum captured value is detected. • DERIV0 - notifies by event or interrupt when a local extreme captured value is detected, see Figure 36-27. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 819 In other modes, an interrupt is only generated on an extreme captured value. Figure 36-26. Capture Action “CAPTMAX” "clear" update COUNT "match" ZERO FaultA Input CC0 Event/ Interrupt Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 820 Note that in RAMP2 and RAMP2A operations, when a new timer/counter cycle starts, the cycle index will automatically change. Figure 36-28. Waveform Generation with Halt and Restart Actions "clear" update "match" COUNT HALT ZERO Restart Restart Fault Input A WO[0] Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 821 When the Fault Detection on Debug Break Detection bit in Debug Control register (DGBCTRL.FDDBD) is written to '1', a non-recoverable Debug Faults State and an interrupt (DFS) is generated when the system goes in debug operation. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 822 Slice 1 DTI1 / SWAP1 acting on port pins (WO[1], WO[WO_NUM/2 +1]) And more generally: • Slice n DTIx / SWAPx acting on port pins (WO[x], WO[WO_NUM/2 +x]) Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 823 Together with pattern generation and the fault extension, this configuration can control up to seven LED strings, with a boost stage. Table 36-5. Example: four compare channels on four outputs • Value OTMX[3] OTMX[2] OTMX[1] OTMX[0] Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 824 DTLS register. When the output changes from high to low (negative edge) it reloads the DTHS register. Figure 36-34. Dead-Time Generator Timing Diagram "dti_cnt" DTILS DTIHS "OTMX output" "DTLS" "DTHS" Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 825 CCx register is read Retrigger Count Capture Overflow Error Debug Fault State Recoverable Faults Non-Recoverable Faults Yes TCCx Event 0 input TCCx Event 1 input Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 826 When a CCx channel is selected as a circular buffer, the related DMA request is not set on a compare match detection, but on start of ramp B. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 827 Figure 36-37. DMA Triggers in DSBOTH Operation Mode and Circular Buffer Enabled Cycle New Parameter Set Old Parameter Set "update" COUNT ZERO CTRLB.DIR DMA_CCx_req DMA Channel i Update Rising DMA_OVF_req DMA Channel j Update Rising Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 828 The TCC can take the following actions on counter Event 1 (TCCx EV1): • Counter re-trigger • Counter direction control • Stop the counter • Decrement the counter on event • Period and pulse width capture Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 829 • Control B Clear and Control B Set registers (CTRLBCLR and CTRLBSET) • Count Value register (COUNT): synchronization is done on demand through READSYNC command (CTRLBSET.CMD) Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 830 Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Required read-synchronization is denoted by the "Read-Synchronized" property in the register description. Related Links Register Synchronization on page 116 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 831: Register Summary

    OVFEO EVCTRL 0x22 23:16 MCEI3 MCEI2 MCEI1 MCEI0 0x23 31:24 MCEO3 MCEO2 MCEO1 MCEO0 0x24 0x25 INTENCLR 15:8 FAULT1 FAULT0 FAULTB FAULTA 0x26 23:16 0x27 Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 832 31:24 CC[25:18] 0x4C CC[1:0] DITHER[5:0] 0x4D 15:8 CC[9:2] 0x4E 23:16 CC[17:10] 0x4F 31:24 CC[25:18] 0x50 CC[1:0] DITHER[5:0] 0x51 15:8 CC[9:2] 0x52 23:16 CC[17:10] 0x53 31:24 CC[25:18] Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 833: Register Description

    Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 834 These bits are not synchronized. Value Name Description Counter Reloaded Prescaler GCLK Reload or reset Counter on next GCLK PRESC Reload or reset Counter on next prescaler clock Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 835 These bits are not synchronized. Table 36-7. Dithering Value Name Description NONE The dithering is disabled. DITH4 Dithering is done every 16 PWM frames. PER[3:0] and CCx[3:0] contain dithering pattern selection. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 836 These bits are used to select the capture or compare operation on channel x. Writing a '1' to CPTENx enables capture on channel x. Writing a '0' to CPTENx disables capture on channel x. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 837 This bit controls one-shot operation of the TCC. When one-shot operation is enabled, the TCC will stop counting on the next overflow/underflow condition or on a stop command. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 838 Writing a '1' to this bit will clear the bit and make the counter count up. Value Description The timer/counter is counting up (incrementing). The timer/counter is counting down (decrementing). Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 839 This bit controls one-shot operation of the TCC. When in one-shot operation, the TCC will stop counting on the next overflow/underflow condition or a stop command. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 840 Writing a '1' to this bit will clear the bit and make the counter count up. Value Description The timer/counter is counting up (incrementing). The timer/counter is counting down (decrementing). Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 841 This bit is cleared when the synchronization of STATUS register between the clock domains is complete. This bit is set when the synchronization of STATUS register between clock domains is started. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 842 CCx bit is available only for existing Compare/Capture Channels. For details on CC channels number, refer to each TCC feature list. This bit is set when the synchronization of CCx register between clock domains is started. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 843 CAPT On rising edge of a valid recoverable Fault n, capture counter value on channel selected by CHSEL[1:0]. INTFLAG.FAULTn flag rises on each new captured value. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 844 Halt action disabled Hardware halt action Software halt action Non-recoverable fault Bit 7 – RESTART: Recoverable Fault n Restart Setting this bit enables restart action for Fault n. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 845 Fault input disabled ENABLE MCEx (x=0,1) event input INVERT Inverted MCEx (x=0,1) event input ALTFAULT Alternate fault (A or B) state at the end of the previous period. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 846 This will override the output matrix [x] and [x+WO_NUM/2], with the low side and high side waveform respectively. Value Description No dead-time insertion override. Dead time insertion override on signal outputs[x] and [x+WO_NUM/2], from matrix outputs[x] signal. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 847 These bits define the value of the enabled override outputs, under non-recoverable fault condition. Bits 7,6,5,4,3,2,1,0 – NREx: Non-Recoverable State x Output Enable These bits enable the override of individual outputs by NRVx value, under non-recoverable fault condition. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 848 Value Description Non-recoverable fault tri-state the output. Non-recoverable faults set the output to NRVx level. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 849 Description The TCC is halted when the device is halted in debug mode. The TCC continues normal operation when the device is halted in debug mode. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 850 This bit is used to enable the overflow/underflow event. When enabled an event will be generated when the counter reaches the TOP or the ZERO value. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 851 Start TC on event Increment TC on EVENT COUNT (async) Count on active state of asynchronous event STAMP Capture overflow times (Max value) FAULT Non-recoverable Fault Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 852 Bits 13,12 – TCINVx: Timer/Counter Event x Invert Enable This bit inverts the event x input. Value Description Input event source x is not inverted. Input event source x is inverted. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 853 Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Debug Fault State Interrupt Disable/Enable bit, which disables the Debug Fault State interrupt. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 854 Writing a '1' to this bit will clear the corresponding Match or Capture Channel x Interrupt Disable/Enable bit, which disables the Match or Capture Channel x interrupt. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 855 Writing a '1' to this bit will clear the Non-Recoverable Fault x Interrupt Disable/Enable bit, which disables the Non-Recoverable Fault x interrupt. Value Description The Non-Recoverable Fault x interrupt is disabled. The Non-Recoverable Fault x interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 856 Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Debug Fault State Interrupt Disable/Enable bit, which enables the Debug Fault State interrupt. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 857 Writing a '1' to this bit will set the corresponding Match or Capture Channel x Interrupt Disable/Enable bit, which enables the Match or Capture Channel x interrupt. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 858 Writing a '1' to this bit will set the Non-Recoverable Fault x Interrupt Disable/Enable bit, which enables the Non-Recoverable Fault x interrupt. Value Description The Non-Recoverable Fault x interrupt is disabled. The Non-Recoverable Fault x interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 859 Bit 2 – CNT: Counter Interrupt Flag This flag is set on the next CLK_TCC_COUNT cycle after a counter event occurs. Writing a '0' to this bit has no effect. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 860 This flag is set on the next CLK_TCC_COUNT cycle after a Non-Recoverable Fault x occurs. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Non-Recoverable Fault x interrupt flag. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 861 This bit is set while an active Non-Recoverable Fault 0 input is present. Bit 9 – FAULTBIN: Recoverable Fault B Input This bit is set while an active Recoverable Fault B input is present. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 862 This bit is set by hardware as soon as non-recoverable Fault x condition occurs. This bit is cleared by writing a one to this bit and when the corresponding FAULTxIN status bit is low. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 863 BOTTOM, the timer/counter restart command must be executed before clearing the corresponding STATEx bit. For further details on timer/counter commands, refer to available commands description (CTRLBSET.CMD). Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 864 Note:  This bit field occupies the MSB of the register, [31:m]. m is dependent on the Resolution bit in the Control A register (CTRLA.RESOLUTION): CTRLA.RESOLUTION Bits [31:m] 0x0 - NONE 31:0 (depicted) 0x1 - DITH4 31:4 0x2 - DITH5 31:5 0x3 - DITH6 31:6 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 865 This register holds the enable status of pattern generation for each waveform output. A bit written to '1' will override the corresponding SWAP output with the corresponding PGVn value. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 866 These bits select the waveform generation operation. The settings impact the top value and control if frequency or PWM waveform generation should be used. These bits are not synchronized. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 867 Setting this bits enables the compare circular buffer option on channel. When the bit is set, CCx register value is copied-back into the CCx register on UPDATE condition. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 868 Note:  This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the Control A register (CTRLA.RESOLUTION): Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 869 CTRLA.RESOLUTION Bits [n:0] 0x0 - NONE 0x1 - DITH4 0x2 - DITH5 0x3 - DITH6 5:0 (depicted) Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 870 Note:  This bit field occupies the MSB of the register, [31:m]. m is dependent on the Resolution bit in the Control A register (CTRLA.RESOLUTION): CTRLA.RESOLUTION Bits [31:m] 0x0 - NONE 31:0 0x1 - DITH4 31:4 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 871 Note:  This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the Control A register (CTRLA.RESOLUTION): CTRLA.RESOLUTION Bits [n:0] 0x0 - NONE 0x1 - DITH4 0x2 - DITH5 0x3 - DITH6 5:0 (depicted) Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 872 This register is the buffer of the PGE register. If double buffering is used, valid content in this register is copied into the PGE register at an UPDATE condition. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 873 Note:  This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the Control A register (CTRLA.RESOLUTION): Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 874 CTRLA.RESOLUTION Bits [n:0] 0x0 - NONE 0x1 - DITH4 0x2 - DITH5 0x3 - DITH6 5:0 (depicted) Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 875 Note:  This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the Control A register (CTRLA.RESOLUTION): Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 876 CTRLA.RESOLUTION Bits [n:0] 0x0 - NONE 0x1 - DITH4 0x2 - DITH5 0x3 - DITH6 5:0 (depicted) Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 877: Trng - True Random Number Generator

    Events connected to the event system can trigger other operations in the system without exiting sleep modes. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 878: Functional Description

    As soon as the TRNG is enabled, the module automatically provides a new 32-bit random number every 84 CLK_TRNG_APB clock cycles. When new data is available, an optional interrupt or event can be generated. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 879 Vector Interrupt Controller for details. Related Links Sleep Mode Controller on page 191 Nested Vector Interrupt Controller on page 44 37.6.4. Events The TRNG can generate the following output event: Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 880 When this bit is '1', the TRNG continues to operate during sleep and any enabled TRNG interrupt source can wake up the CPU. 37.6.6. Synchronization Not applicable. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 881: Register Summary

    Enable-protection is denoted by the "Enable-Protected" property in each individual register description. Refer to PAC - Peripheral Access Controller and Synchronizationfor details. Related Links PAC - Peripheral Access Controller on page 50 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 882 The TRNG is halted during standby sleep mode. The TRNG is not stopped in standby sleep mode. Bit 1 – ENABLE: Enable Value Description The TRNG is disabled. The TRNG is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 883 Description Data Ready event output is disabled and an event will not be generated. Data Ready event output is enabled and an event will be generated. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 884 Writing a '1' to this bit will clear the Data Ready Interrupt Enable bit, which disables the corresponding interrupt request. Value Description The DATARDY interrupt is disabled. The DATARDY interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 885 Writing a '1' to this bit will set the Data Ready Interrupt Enable bit, which enables the corresponding interrupt request. Value Description The DATARDY interrupt is disabled. The DATARDY interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 886 This flag is cleared by writing a '1' to the flag or by reading the DATA register. Writing a '0' to this bit has no effect. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 887 DATA[31:24] Access Reset DATA[23:16] Access Reset DATA[15:8] Access Reset DATA[7:0] Access Reset Bits 31:0 – DATA[31:0]: Output Data These bits hold the 32-bit randomly generated output data. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 888: Aes - Advanced Encryption Standard

    Supports Counter with CBC-MAC (CCM/CCM*) mode for authenticated encryption • 8, 16, 32, 64, 128-bit data sizes possible in CFB mode • Optional (parameter) Galois Counter mode (GCM) encryption and authentication Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 889: Block Diagram

    ADD ROUND KEY DECRYPTION ENCRYPTION ADD ROUND KEY INV MIX COLUMNS SUBBYTES INV SHIFT ROWS SHIFT ROWS INV SUBBYTES ADD ROUND KEY ADD ROUND KEY CIPHERTEXT PLAINTEXT Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 890: Signal Description

    CPU through interrupts or similar, improper operation or data loss may result during debugging. The AES module can be forced to halt operation during debugging. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 891: Functional Description

    Nr is the number of rounds, depending on the key length. 38.6.2. Basic Operation 38.6.2.1. Initialization The following register is enable-protected: • Control A (CTRLA) Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 892 (DATABUFPTR = 1) output buffer registers (see see Table 38-1). The Encryption Complete bit (INTFLAG.ENCCMP) is cleared by hardware after the processed data has been read from the relevant output buffer registers. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 893 Also software read from the Output Data Register (DATA) is not required to clear the ENCCMP flag. The ENCCMP flag is automatically cleared by writing into the Input Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 894 AES module’s throughput. In short, the throughput is highest with all the countermeasures disabled. On the other hand, with all of the countermeasures enabled, the best protection is achieved but the throughput is worst. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 895 AES Counter mode of operation for encryption. Authenticity of the confidential data is assured through the GHASH engine. Refer to the NIST Special Publication 800-38D Recommendation for more complete information. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 896 CIPH(K) CIPH(K) Plaintext 1 Plaintext 2 Ciphertext 1 Ciphertext 2 Encryption GF128Mult(H) GF128Mult(H) GF128Mult(H) Len (A) || Len (C) Auth Data 1 GF128Mult(H) Auth Tag Authentication Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 897 Continue steps 4 to 7 for remaining Authentication Header. Note: If the Auth data is less than 128 bit, it has to be padded with zero to make it 128 bit aligned. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 898 Load (J0+1) in INTVECTx register. • Load plain text in DATA register. • Wait for INTFLAG.ENCCMP to be set. • AES Hardware generates output in DATA register. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 899 Set CTRLB.NEWMSG and CTRLB.START to start the Counter mode operation. • Wait for INTFLAG.ENCCMP to be set. • AES Hardware generates the GCM Tag output in DATA register. 38.6.4. Synchronization Not applicable. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 900: Register Summary

    31:24 KEYWORD[31:24] KEYWORD[7:0] 15:8 KEYWORD[15:8] KEYWORDx4 23:16 KEYWORD[23:16] 31:24 KEYWORD[31:24] KEYWORD[7:0] 15:8 KEYWORD[15:8] KEYWORDx5 23:16 KEYWORD[23:16] 31:24 KEYWORD[31:24] KEYWORD[7:0] 15:8 KEYWORD[15:8] KEYWORDx6 23:16 KEYWORD[23:16] 31:24 KEYWORD[31:24] Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 901 31:24 HASHKEY[31:24] 0x64 HASHKEY[7:0] 0x65 15:8 HASHKEY[15:8] HASHKEYx2 0x66 23:16 HASHKEY[23:16] 0x67 31:24 HASHKEY[31:24] 0x68 HASHKEY[7:0] 0x69 15:8 HASHKEY[15:8] HASHKEYx3 0x6A 23:16 HASHKEY[23:16] 0x6B 31:24 HASHKEY[31:24] Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 902: Register Description

    Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 903 Countermeasure4 disabled 1XXX CTYPE4 enabled Countermeasure4 enabled Bit 14 – XORKEY: XOR Key Value Description No effect The user keyword gets XORed with the previous keyword register content. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 904 16-bit data block 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode 8-bit data block 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 905 Writing a '1' to SWRST will always take precedence, meaning that all other writes in the same write operation will be discarded. Value Description There is no reset operation ongoing The reset operation is ongoing Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 906 Setting this bit indicates start of new message to the module. Bit 0 – START: Start Encryption/Decryption Value Description No action Start encryption / decryption in manual mode. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 907 Writing a '1' to this bit will clear the Encryption Complete Interrupt Enable bit, which disables the Encryption Complete interrupt. Value Description The Encryption Complete interrupt is disabled. The Encryption Complete interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 908 Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Encryption Complete Interrupt Enable bit, which enables the Encryption Complete interrupt. Value Description The Encryption Complete interrupt is disabled. The Encryption Complete interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 909 Reading from the data register (DATAx) when LOD = 0. Writing into the data register (DATAx) when LOD = 1. Reading from the Hash Key register (HASHKEYx). Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 910 Writing to this field changes the value of the input data pointer, which determines which of the four data registers is written to/read from when the next write/read to the DATA register address is performed. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 911 Writing a '1' to this bit allows the AES to continue normal operation during debug mode. This bit can only be changed while the AES is disabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 912 KEYWORD5/KEYWORD7.KEYWORD to the last one. Note:  By setting the XORKEY bit of CTRLA register, keyword will update with the resulting XOR value of user keyword and previous keyword content. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 913 DATABUFPTR.DATPTR field. Note:  Both input and output shares the same data buffer. Reading DATA register will return 0’s when AES is performing encryption or decryption operation. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 914 Initialization Vector from being read by another application. For CBC, OFB, and CFB modes, the Initialization Vector corresponds to the initialization vector. For CTR mode, it corresponds to the counter value. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 915 The four 32-bit HASHKEYx registers contain the 128-bit Hash Key value computed from the AES KEY. The Hash Key value can also be programmed offering single GF128 multiplication possibilities. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 916 The four 32-bit Hash Word registers GHASHxcontain the GHASH value after GF128 multiplication in GCM mode. Writing a new key to KEYWORDx registers causes GHASHx to be initialized with zeroes. These registers can also be programmed. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 917 This register contains the length in bytes of the Cipher text that is to be processed. This is programmed by the user in GCM mode for Tag generation. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 918 Access Reset RANDSEED[7:0] Access Reset Bits 31:0 – RANDSEED[31:0]: Random Seed A write to this register corresponds to loading a new seed into the Random number generator. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 919: Usb - Universal Serial Bus

    Supports 8 IN endpoints and 8 OUT endpoints – No endpoint size limitations – Built-in DMA with multi-packet and dual bank for all endpoints – Supports feedback endpoint – Supports crystal less clock Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 920: Usb Block Diagram

    The USB module requires a GCLK_USB of 48 MHz ± 0.25% clock for low speed and full speed operation. To follow the USB data rate at 12Mbit/s in full-speed mode, the CLK_USB_AHB clock should be at minimum 8MHz. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 921 USB Pad Calibration register (PADCAL) by software, before enabling the USB, to achieve the specified accuracy. Refer to NVM Software Calibration Area Mapping for further details. For details on Pad Calibration, refer to Pad Calibration (PADCAL) register. Related Links Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 922: Functional Description

    Endpoint data can be placed anywhere in the device RAM. The USB controller accesses these endpoints directly through the AHB master (built-in DMA) with the help of the endpoint descriptors. The base Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 923 Device Interrupt Flag register (INTFLAG.SOF) is set. If there is a CRC or bit-stuff error, the Frame Number Error status flag (FNUM.FNCERR) in the FNUM register is set. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 924 (EPCFG) of the addressed output endpoint. If the type of the endpoint (EPCFG.EPTYPE0) is not set to OUT, the USB module returns to idle and waits for the next token packet. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 925 PCKSIZE.SIZE after the transaction has completed, and EPSTATUS.DTGLOUT will be toggled if the endpoint is not isochronous. If the updated PCKSIZE.BYTE_COUNT is equal to PCKSIZE.MULTI_PACKET_SIZE (i.e. the last transaction), EPSTATUS.BK1RDY/BK0RDY, and EPINTFLAG.TRCPT0/TRCPT1 will be set. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 926 (banks) for a given endpoint in a single direction. The direction is selected by enabling one of the IN or OUT direction in EPCFG.EPTYPE0/1 and configuring the opposite direction in EPCFG.EPTYPE1/0 as Dual Bank. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 927 When the controller sends the Upstream Resume INTFLAG.WAKEUP is set and INTFLAG.SUSPEND is cleared. The CTRLB.UPRSM is cleared at the end of the transmitting Upstream Resume. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 928 Interrupt Enable bit in INTENCLR/SET (INTENCLR/SET.LPMNYET) is set. If the LPM transaction is responded with a STALL or no handshake, no flag is set, and the transaction is ignored. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 929 INTFLAG.SOF INTENSET.SOF INTFLAGA.MSOF INTENSET.MSOF INTFLAG.SUSPEND INTENSET.SUSPEND Asynchronous interrupt The WAKEUP is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 930: Register Summary

    Reserved 0x16 Reserved 0x17 Reserved 0x1A Reserved 0x1B Reserved 0x1E Reserved 0x1F Reserved Table 39-2. Device Endpoint Register n Offset Name Bit Pos. 0x1m1 Reserved 0x1m2 Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 931 0x02 23:16 ADD[23:16] 0x03 31:24 ADD[31:24] 0x04 BYTE_COUNT[7:0] 0x05 15:8 MULTI_PACKET_SIZE[1:0] BYTE_COUNT[13:8] PCKSIZE 0x06 23:16 MULTI_PACKET_SIZE[9:2] 0x07 31:24 AUTO_ZLP SIZE[2:0] MULTI_PACKET_SIZE[13:10] 0x08 Reserved 0x09 Reserved 15:8 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 932: Register Description

    Protection, PAC - Peripheral Access Controller and GCLK Synchronization for details. Related Links PAC - Peripheral Access Controller on page 50 39.8.1. Communication Device Host Registers Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 933 CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. This bit is Write-Synchronized. Value Description There is no reset operation ongoing. The reset operation is ongoing. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 934 This bit is cleared when the synchronization of SWRST register between the clock domains is complete. This bit is set when the synchronization of SWRST register between clock domains is started. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 935 Bits 1:0 – CQOS[1:0]: Configuration Quality of Service These bits define the memory priority access during the endpoint or pipe read/write configuration operation. Refer to SRAM Quality of Service. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 936 Corresponds to the Idle and Active states. 0x04 SUSPEND (L2) 0x08 SLEEP (L1) 0x10 DNRESUME Down Stream Resume. 0x20 UPRESUME Up Stream Resume. 0x40 RESET USB lines Reset. Others Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 937 Bits 31:0 – DESCADD[31:0]: Descriptor Address Value These bits define the base address of the main USB descriptor in RAM. The two least significant bits must be written to zero. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 938 These bits calibrate the NMOS output impedance of DP/DM drivers. Bits 4:0 – TRANSP[4:0]: Trimmable Output Driver Impedance P These bits calibrate the PMOS output impedance of DP/DM drivers. 39.8.2. Device Registers - Common Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 939 Disable the “NO_REPLY” feature: Any transaction to endpoint 0 will be handled according to the USB2.0 standard. Enable the “NO_REPLY” feature: Any transaction to endpoint 0 will be ignored except SETUP. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 940 The device is attached to the USB bus so that communications may occur. It is the default value at reset. The internal device pull-ups are disabled, removing the device from the USB bus. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 941 Writing a one will activate the DADD field (USB device address). Bits 6:0 – DADD[6:0]: Device Address These bits define the device address. The DADD register is reset when a USB reset is received. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 942 FS-K or LS-J State Bits 3:2 – SPEED[1:0]: Speed Status These bits define the current speed used of the device SPEED[1:0] SPEED STATUS Low-speed mode Full-speed mode Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 943 These bits are cleared upon receiving a USB reset or at the beginning of each Start-of-Frame (SOF interrupt). These bits are updated with the micro-frame number information as provided from the last MSOF packet even if a corrupted MSOF is received. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 944 Writing a zero to this bit has no effect. Writing a one to this bit will clear the RAM Access interrupt Enable bit and disable the corresponding interrupt request. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 945 The End of Reset interrupt is disabled. The End of Reset interrupt is enabled and an interrupt request will be generated when the End of Reset interrupt Flag is set. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 946 Value Description The Suspend interrupt is disabled. The Suspend interrupt is enabled and an interrupt request will be generated when the Suspend interrupt Flag is set. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 947 Writing a one to this bit will set the RAM Access Enable bit and enable the corresponding interrupt request. Value Description The RAM Access interrupt is disabled. The RAM Access interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 948 Writing a one to this bit will set the Start-of-Frame interrupt Enable bit and enable the corresponding interrupt request. Value Description The Start-of-Frame interrupt is disabled. The Start-of-Frame interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 949 Writing a one to this bit will set the Suspend interrupt Enable bit and enable the corresponding interrupt request. Value Description The Suspend interrupt is disabled. The Suspend interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 950 This flag is set when the USB sends a resume signal called “Upstream Resume” and will generate an interrupt if INTENCLR/SET.UPRSM is one. Writing a zero to this bit has no effect. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 951 This flag is set when a USB “Suspend” idle state has been detected for 3 frame periods (J state for 3 ms) and will generate an interrupt if INTENCLR/SET.SUSPEND is one. Writing a zero to this bit has no effect. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 952 The flag EPINT[n] is set when an interrupt is triggered by the EndPoint n. See EPINTFLAGn register in the device EndPoint section. This bit will be cleared when no interrupts are pending for EndPoint n. 39.8.3. Device Registers - Endpoint Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 953 Bank0 is enabled and configured as Interrupt OUT. Bank0 is enabled and configured as Dual Bank IN (Endpoint type is the same as the one defined in EPTYPE1) 0x6-0x7 Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 954 Bit 0 – DTGLOUT: Data Toggle OUT Writing a zero to this bit has no effect. Writing a one to this bit will clear the EPSTATUS.DTGLOUT bit. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 955 Bit 0 – DTGLOUT: Data Toggle OUT Writing a zero to this bit has no effect. Writing a one to this bit will set the EPSTATUS.DTGLOUT bit. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 956 Writing a zero to the bit EPSTATUSCLR.STALLRQ0 will clear this bit. Writing a one to the bit EPSTATUSSET.STALLRQ0 will set this bit. This bit is cleared by hardware when receiving a SETUP packet. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 957 The PID of the next expected OUT transaction will be zero: data 0. The PID of the next expected OUR transaction will be one: data 1. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 958 This flag is set when a transfer fail occurs and will generate an interrupt if EPINTENCLR/SET.TRFAIL1 is one. EPINTFLAG.TRFAIL1 is set for a single bank IN endpoint or double bank IN/OUT endpoint when current bank is "1". Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 959 "0". Writing a zero to this bit has no effect. Writing a one to this bit clears the TRCPT0 Interrupt Flag. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 960 Bit 3 – TRFAIL1: Transfer Fail 1 Interrupt Enable The user should look into the descriptor table status located in ram to be informed about the error condition : ERRORFLOW, CRC. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 961 The Transfer Complete bank 0 interrupt is disabled. The Transfer Complete bank 0 interrupt is enabled and an interrupt request will be generated when the Transfer Complete 0 Interrupt Flag is set. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 962 Writing a one to this bit will enable the Transfer Fail interrupt. Value Description The Transfer Fail interrupt is disabled. The Transfer Fail interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 963 Writing a one to this bit will enable the Transfer Complete 1 interrupt. 0.2.4 Device Registers - Endpoint RAM Value Description The Transfer Complete bank 0 interrupt is disabled. The Transfer Complete bank 0 interrupt is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 964 2 x 0xn0 ADDR Reserved +0x01B STATUS_BK +0x01A Bank1 Reserved +0x018 PCKSIZE +0x014 ADDR +0x010 +0x00B Reserved Bank0 +0x00A STATUS_BK +0x008 EXTREG +0x004 PCKSIZE DESCADD +0x000 ADDR Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 965 These bits define the data pointer address as an absolute word address in RAM. The two least significant bits must be zero to ensure the start address is 32-bit aligned. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 966 Bits 30:28 – SIZE[2:0]: Endpoint size These bits contains the maximum packet size of the endpoint. Value Description 8 Byte 16 Byte 32 Byte 64 Byte 128 Byte 256 Byte Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 967 For IN endpoints, BYTE_COUNT holds the number of bytes to be sent in the next IN transaction. For OUT endpoint or SETUP endpoints, BYTE_COUNT holds the number of bytes received upon the last OUT or SETUP transaction. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 968 ACK to a LPM transaction. See Section 2.1.1 Protocol Extension Token in the reference document “ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum”. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 969 This bit is set when a CRC error has been detected in an isochronous OUT endpoint bank. 0.2.5 Host Registers - Common Value Description No CRC Error. CRC Error detected. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 970: Ccl - Configurable Custom Logic

    Subsequent LUT Output • Output can be connected to IO pins or Event System • Optional synchronizer, filter, or edge detector available on each LUT output Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 971: Block Diagram

    This peripheral can continue to operate in any sleep mode where its source clock is running. Events connected to the event system can trigger other operations in the system without exiting sleep modes. Related Links PM – Power Manager on page 188 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 972: Functional Description

    Configurable Custom Logic (CCL) is a programmable logic block that can use the device port pins, internal peripherals, and the internal Event System as both input and output channels. The CCL can Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 973 Figure 40-2. Truth Table Output Value Selection TRUTH[0] TRUTH[1] TRUTH[2] TRUTH[3] TRUTH[4] TRUTH[5] TRUTH[6] LUTCTRL (ENABLE) TRUTH[7] IN[2:0] Table 40-1. Truth Table of LUT IN[2] IN[1] IN[0] TRUTH[0] TRUTH[1] TRUTH[2] Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 974 LUT0 and LUT1. The sequential selection for each LUT follows the formula: IN 2N+1 � = SEQ � With N representing the sequencer number and i=0,1,2 representing the LUT input index. For details, refer to Sequential Logic. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 975 The CCL includes an edge detector. When the event is received, an internal strobe is generated when a rising edge is detected. The pulse duration is one GCLK_CCL clock cycle. The following steps ensure proper operation: Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 976 The output of comparator 0 is available on even LUTs ("LUT(2x)": LUT0, LUT2) and the comparator 1 output is available on odd LUTs ("LUT(2x+1)": LUT1, LUT3), as shown in the figure below. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 977 LUT input (i.e., IN0 is connected to WO0, IN1 to WO1, and IN2 to WO2), as shown in the figure below. Before selecting the waveform outputs, the TCC must be configured first. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 978 APB clock after the corresponding LUT is disabled, all internal filter logic is cleared. Note:  Events used as LUT input will also be filtered, if the filter is enabled. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 979 When the DFF is selected, the D-input is driven by the even LUT output (LUT2x), and the G-input is driven by the odd LUT output (LUT2x+1), as shown in Figure 40-14. Figure 40-14. D Flip Flop Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 980 When the DLATCH is selected, the D-input is driven by the even LUT output (LUT2x), and the G-input is driven by the odd LUT output (LUT2x+1), as shown in Figure 40-14. Figure 40-16. D-Latch LUT2x LUT(2x+1) Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 981 Writing a '0' to this bit disables the corresponding action on input event. Refer to EVSYS – Event System for details on configuration. Related Links Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 982 LUT output will be forced to zero in STANDBY mode. In all other cases, the TRUTH table decoder will continue operation and the LUT output will be refreshed accordingly. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 983: Register Summary

    Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 984 Writing a '1' to this bit resets all registers in the CCL to their initial state. Value Description There is no reset operation ongoing. The reset operation is ongoing. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 985 These bits select the sequential configuration: Sequential Selection Value Name Description DISABLE Sequential logic is disabled D flip flop JK flip flop LATCH D latch RS latch 0x5 - 0xF Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 986 LUT incoming event is disabled. LUT incoming event is enabled. Bit 20 – INVEI: Inverted Event Input Enable Value Description Incoming event is not inverted. Incoming event is inverted. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 987 I/O pin input source AC input source TC input source ALTTC Alternative TC input source TCC input source SERCOM SERCOM input source 0xA - 0xF - Reserved Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 988: Adc - Analog-To-Digital Converter

    Hardware gain and offset compensation • Averaging and oversampling with decimation to support up to 16-bit result • Selectable sampling time • Flexible Power / Throughput rate management Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 989: Block Diagram

    I/O Multiplexing and Considerations on page 27 41.5. Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 990 When the CPU is halted in debug mode the ADC will halt normal operation. The ADC can be forced to continue operation during debugging. Refer to DBGCTRL for details. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

  • Page 991: Functional Description

    The ADC is reset by writing a '1' to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the ADC, except DBGCTRL, will be reset to their initial state, and the ADC will be disabled. Refer to CTRLA for details. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 992 Two external references are available. The supply accepted on these pins is from 1.0V to VDD . Four internal inputs are also available. Refer to REFCTRL for further details on available selections. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 993 ADC clock frequency from the DATA CLK_ADC internal prescaler: f / 2^(1 + CTRLB.PRESCALER) CLK_ADC GCLK_ADC Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 994 Control C register (CTRLC.RESSEL) must be set. Table 41-1. Accumulation Number of AVGCTRL. Number of Final Result Automatic Accumulated SAMPLENUM Automatic Right Precision Division Factor Samples Shifts 12 bits 13 bits Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 995 Number Result Division Samples Precision Right of Right Precision Factor Shifts Shifts 12 bits 12 bits 12 bits 12 bits 12 bits 12 bits 12 bits Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 996 If additional inputs must be scanned, the ADC will automatically start a new conversion on the next input present in the sequence list. Note that if SEQCTRL register has no bits set to '1', the conversion is done with the selected MUXPOS input. Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 997 Figure 41-8.  ADC Timing Correction Enabled START CONV0 CONV1 CONV2 CONV3 CORR0 CORR1 CORR2 CORR3 41.6.3. DMA Operation The ADC generates the following DMA request: Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 998 This is done by setting the corresponding Event Invert Enable bit in Event Control register (EVCTRL.xINV=1). Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 999 Gain correction register (GAINCORR) • Offset Correction register (OFFSETCORR) • Software Trigger register (SWTRIG) Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Related Links Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...
  • Page 1000 Register Synchronization on page 116 1000 Atmel SAM L22G / L22J / L22N [DATASHEET] Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016...

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