Post Boot Behavior; Rom Init - ADIC Scalar 1000 User Manual

For the scalar 1000 and 10k
Hide thumbs Also See for Scalar 1000:
Table of Contents

Advertisement

SNC 5100
POST Error Codes
The Power-On-Self-Test (POST) is responsible for testing the integrity of the
processor's SDRAM. After testing SDRAM POST will attempt to transfer
control to either the default bootrom image or an alternate image.
POST can also download binary images over the service port and write them to
flash memory. This enables POST to perform a minimal amount of emergency
recovery from FLASH errors.

POST Boot Behavior

ROM Init

Figure 10 ROM Init
After applying power the ERR LED will illuminate.
At this time
code initializes the processor's internal registers and
postInit
subsystems, including the SDRAM controller.
The processor's internal RAM is used as a tiny-stack for this stage of POST.
Control is then passed to the
routine for the SDRAM memory.
IpostMain
POST Boot Behavior
197
6-00020-02

Advertisement

Table of Contents
loading

This manual is also suitable for:

Scalar 10kSnc 5100

Table of Contents