Digital Interface - Texas Instruments ADS1278EVM-CVAL User Manual

ADS1278EVM-CVAL Hardware Details
Analog input sources (Channels 5-8) are connected directly to J1. These inputs can be filtered by
installing passive components in the option filter circuitry. By default, the resistors are populated with 0-Ω
resistors and the capacitors are not installed. No circuitry is provided to buffer these signals before
connecting to the converter.
Description
Analog Input Channel 4 Negative
Analog Input Channel 3 Negative
Analog Input Channel 2 Negative
Analog Input Channel 1 Negative
Analog Ground
Analog Ground
Analog Ground
Not used for this design
Analog Ground
Analog Ground
(1)
Pin 1 is top left-hand corner, located next to reference designator.
Description
Not used for this design
Analog Input Channel 8 Negative
Analog Input Channel 7 Negative
Analog Input Channel 6 Negative
Analog Input Channel 5 Negative
(1)
Pin 1 is top right-hand corner, located next to reference designator.
5.5

Digital Interface

The digital signals are controlled via DSP interface or I
allow control via hardware or software methods. See
operation. The digital control signals can be applied directly to the EVM or by connecting the EVM to a
DSP or micro controller interface board, the
available from Texas Instruments.
5.5.1 Digital Format Control
The ADS1278-SP allows the serial interface to be used in two different formats: an SPI-compatible mode
and a frame-sync format. Switch S6 is populated with jumpers to select between these two formats:
• SPI format configures the signals as follows:
– The SCLK input of the converter is driven by the serial port signal CLKX, pin J4.3.
– The signal from the selected source for the clock (see
(J4.5) allowing the serial port of a processor to be synchronized to the converters master clock.
– The signal from the selected clock source is routed to the CLK input of the converter.
– Port P10 of the I
switch S12 can be read back by software.
18
ADS1278EVM-CVAL Evaluation Module User's Guide
Table 7. J3: Primary Analog Interface Pinout
Signal Designator
AINN4 J3.1
AINN3 J3.3
AINN2 J3.5
AINN1 J3.7
AGND J3.9
AGND J3.11
AGND J3.13
Not Connected J3.15
AGND J3.17
AGND J3.19
Table 8. J1: Secondary Analog Interface Pinout
Signal Designator
Not Connected J1.1
AINN8 J1.3
AINN7 J1.5
AINN6 J1.7
AINN5 J1.9
5-6K
2
C port expander U8 is connected to a logic high level, so that the position of
Copyright © 2018, Texas Instruments Incorporated
Signal
(1)
J3.2 AINP4
J3.4 AINP3
J3.6 AINP2
J3.8 AINP1
J3.10 Not Connected
J3.12 Analog Ground
J3.14 Not Connected
J3.16 Not Connected
J3.18 EXTREFN
J3.20 EXTREFP
Signal
(1)
J1.2 Not Connected
J1.4 AINP8
J1.6 AINP7
J1.8 AINP6
J1.10 AINP5
2
C ICs on the EVM. Some of the digital control pins
Section 5.2 for details on these pins and their
Interface, or HPA-MCUInterface
Clock Source) is connected to the CLKR pin
www.ti.com
Description
Analog Input Channel 4 Positive
Analog Input Channel 3 Positive
Analog Input Channel 2 Positive
Analog Input Channel 1 Positive
Not used for this design
AGND
Not used for this design
Not used for this design
External Reference negative input
External Reference positive input
Description
Not used for this design
Analog Input Channel 8 Positive
Analog Input Channel 7 Positive
Analog Input Channel 6 Positive
Analog Input Channel 5 Positive
boards which are
SBAU324 – September 2018
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