Texas Instruments ADS1278EVM-CVAL User Manual page 22

Schematic and Bill of Materials
6.1 ADS1278EVM-CVAL EVM Schematics
AVDD
DVDD
IOVDD
C20
C41 AVDD_1
0.1uF
C42
0.1uF
AVDD_1
C45
0.1uF
0.1uF
AGND
REFP
REFN
CHAN-P[1..4]
CHAN-P[1..4]
CHAN-N[1..4]
CHAN-N[1..4]
CHAN-N[5..8]
CHAN-N[5..8]
CHAN-P[5..8]
CHAN-P[5..8]
22
ADS1278EVM-CVAL Evaluation Module User's Guide
= 5V x 0.145A = 0.725W
= 1.8V x 0.030A = 0.054W
= 3.3V x 0.001A = 0.033W
DVDD_26
C43
U4
AVDD_1
1µF
7 36
AVDD DVDD
8 35 DGND
AVDD DVDD
55
AVDD
AVDD_1
56 30
AVDD IOVDD IOVDD_22_23
70 29
AVDD IOVDD
71 28
C46
AVDD IOVDD
78 27
AVDD IOVDD
79
AVDD
0.1uF
VCOM 73 52 PWDN1 DGND
VCOM PWDN1
TP3 51 PWDN2
PWDN2
74 50 PWDN3
VREFP PWDN3
75 49 PWDN4
VREFN PWDN4
48 PWDN5
PWDN5
TP2
47 PWDN6
PWDN6
CHAN-P1 4 46 PWDN7
AINP1 PWDN7
CHAN-N1 PWDN8
5 45
AINN1 PWDN8
PWDN[1..8]
PWDN[1..8]
CHAN-P2 1 44 GPIO0
AINP2 MODE0
CHAN-N2 2 43 GPIO1
AINN2 MODE1
CHAN-P3 83 42 GPIO2
AINP3 FORMAT0
CHAN-N3 84 41 GPIO3
AINN3 FORMAT1
40 GPIO4
FORMAT2
CHAN-P4 80 GPIO[0..4]
AINP4 GPIO[0..4]
CHAN-N4 81
AINN4
39
DRDY/FSYNC
CHAN-P5 67
AINP5
R13 47
CHAN-N5 68 38
AINN5 SCLK
CHAN-P6
64 37
AINP6 CLK
CHAN-N6
65
AINN6
25 J2
DOUT1
CHAN-P7 61 24 1 2
AINP7 DOUT2
CHAN-N7 62 23 3 4
AINN7 DOUT3
22 5 6
DOUT4
CHAN-P8 58 21 7 8
AINP8 DOUT5
CHAN-N8 59 20
AINN8 DOUT6
19
DOUT7
18
DOUT8
3
AGND
6 17
AGND DIN
9
AGND
10 16
AGND SYNC
11
AGND
53 15
AGND CLKDIV CLKDIV
R41
54
AGND
R40
57 14
AGND TEST1 47
R25
60 13
1.0k
AGND TEST0
63 IOVDD
47
AGND
R19
66 34 DGND
AGND DGND
69 33
100k
AGND DGND
72 32
AGND DGND
76 31
AGND DGND
77 26
AGND DGND
82 12
AGND DGND
ADS1278HFQ/EM
AGND DGND
AVDD
6
TP5
VCOM 5
C11
0.1uF
AGND AGND
C26
10uF
AGND AVDD_1
DVDD_26
C57
DGND 10uF
IOVDD
R55
0
R53, R54, R55 are available for current monitoring
Figure 12. Schematic01
Copyright © 2018, Texas Instruments Incorporated
JP1
R12
47
JP2 S6 IOVDD
R44
SW_IND 1 16
SW_IND
100k
2 15
TP6
3 14
DGND
4 13
TP8
5 12
6 11
7 10
8 9
IOVDD
C54
U12 IOVDD
0.1uF
DGND 8 7
VCC PRE
R16 47
U10A
6
CLR
2 4 1
CLK
SN74LVC1G04MDBVREP 5
Q
2
D
U10B 3
Q
SN74LVC1G04MDBVREP
1 4
NC GND
IOVDD
5 3
VCC GND
SN74LV C2G74MDCUTEP DGND
C51
0.1uF DGND
DGND
U13
3 4
IN0 Y
1
IN1
6
IN2
IOVDD
5 2
VCC GND
C56
0.1uF
SN74LV C1G97IDCKREP DGND
DGND U6
IOVDD
8
VCC
U2B
OPA2350EA/250 5 1
Y A
7 IOVDD 2
CM B
3
Y
AVDD 6
A/B
C27
0.1uF
4 7
GND G
C44
0.1uF
SN74LV C2G157DCTR
DGND DGND
AGND
AVDD
J5
1 2
R53
3 4
0 5 6
R54
7 8
0
9 10
AGND
IOVDD_22_23
TP7 TP4 TP1 TP11
DGND AGND
GPIO[0..4]
GPIO[0..4]
J4
SYNC GPIO0
1 2
SCLK
3 4
5 6 GPIO1
7 8 GPIO2
9 10
11 12 GPIO3
13 14 GPIO4
15 16 SCL
SCL
17 18
19 20 SDA
SDA
R31
470k
DGND
DGND
IOVDD
R51 47k
INT/EXT CLK SOURCE
47k
R52
JP4 = HW/SW CTRL (HW/SW)
JP5 = HW SEL (INT/EXT)
(see table below)
1
2
JP4 JP4 JP5 Setting
1 JP5
2 DGND OFF ON Hardware External
OFF OFF Hardware Internal
ON x Software Control (GPIO5)
DGND
R30
470k
Y1 IOVDD C28
1 4
EOH VCC
DGND 0.1uF
2 3
GND OUT
DGND
CB3LV-3I-27M0000
DGND
SBAU324 – September 2018
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