Digital Interface; Gpio - Texas Instruments ADS1258EVM-PDK User Manual

Digital Interface

4 Digital Interface
As noted in Section 1, the EVM interfaces with the PHI and communicates with the host over USB.
shows how the PHI communicates with two devices on the EVM: the ADS1258 using the serial peripheral
interface (SPI) and the EEPROM using the inter-integrated circuit (I
preprogrammed with the information required to configure and initialize the ADS1258EVM. When the hardware
is initialized, no further communication with the EEPROM is necessary and this device can be ignored by the
user.
PHI Connector &
SPI Interface
START
DIN
CS
SCLK
DRDY
ADC
MCLK_OUT
DOUT
RESET
PWDN
EVM_DVDD
C9
10uF
GND
Figure 4-1. ADS1258EVM Digital Interface Connections (SPI and I
The ADS1258 communicates with the PHI using an SPI interface in mode 00 (CPOL = 0, CPHA = 0). Header
J6 in Figure 4-1 provides test points for all digital signals to and from the PHI controller. The test points can be
connected to a logic analyzer for convenient visualization of the digital signals. These test points can also be
used to communicate with the ADS1258EVM using an external controller.

4.1 GPIO

The ADS1258 has eight dedicated GPIO pins. The EVM connects a 100-kΩ pulldown resistor to each GPIO pin.
These resistors prevent the pin voltage from floating because the default ADC settings configure each GPIO as
an input. Additionally, 49.9-Ω resistors are placed in series with each GPIO pin to limit current flow into the ADC.
All eight GPIO pins are terminated at header J7 for easy connection to external circuitry if desired.
shows the GPIO circuitry.
GND
DVDD
10 ADS1258EVM-PDK Evaluation Module
J5
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
R62 49.9 26
26
CAP_CLK
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
EVM_ID_SDA
56
56
EVM_ID_SCL 58
58
60
60
MP1
GND GND
MP2
GND GND
GND
J7
1
2
3
4
5
6
7
8
9
10
R51 R52 R53
100k 100k 100k
Figure 4-2. ADS1258EVM GPIO Circuit and Header
Copyright © 2023 Texas Instruments Incorporated
2
C) interface. The EEPROM comes
EVM_REG_5V5
EVM_ID_PWR
1
1
3
3
5
5
7
7
9
9
11
GND
11
13
13
15
15
17
17
19
19
21
21
GND
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49 WP
49
51
51
EVM_ID_PWR
53
ADC
53
55
55
57
57
R21
59
59
0
MP3
C10
MP4
10uF
GND GND
R54 R55 R56 R57 R58
100k 100k 100k 100k 100k
GND
www.ti.com
Figure 4-1
EVM ID EEPROM
EVM_ID_PWR
U2
R3
1 8
10k
A0 VCC
WP
2 7
A1 WP
EVM_ID_SCL
3 6
A2 SCL
EVM_ID_SDA
4 5
VSS SDA
BR24G32FVT-3AGE2
Digital Signal Header
CS
START
J6
1
DRDY
3
5
DOUT
7
9
DIN
11
13
SCLK
15
17
MCLK_OUT
RESET
PWDN
2
C)
Figure 4-2
R41 49.9 GPIO7
R42 49.9 GPIO6
R43 49.9 GPIO5
R44 49.9 GPIO4
R45 49.9 GPIO3
R48 49.9 GPIO2
R49 49.9 GPIO1
R50 49.9 GPIO0
SBAU126E – MAY 2007 – REVISED JUNE 2023
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C2
100nF
GND
2
4
6
8
10
12
14
16
18
GND