Texas Instruments ADS127L18 User Manual

Texas Instruments ADS127L18 User Manual

Evaluation module

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EVM User's Guide: ADS127L18EVM-PDK
ADS127L18EVM-PDK Evaluation Module
Description
The ADS127L18 is an eight channel, 24-bit,
simultaneous sampling delta-sigma (ΔΣ) analog-to-
digital converter (ADC), supporting data rates up
to 512 kSPS (wideband filter) and data rates up
to 1.365 MSPS (low-latency filter). The ADS127L18
offers excellent ac and dc performance, along with
multiple internal digital filter options. The evaluation
kit includes the ADS127L18EVM board and the
precision host interface (PHI) controller board that
enables the accompanying computer software to
communicate with the ADC over the USB for data
capture, configuration, and analysis.
Get Started
1. Order ADS127L18EVM-PDK from
2. Download the
ADS127L18EVM-PDK-GUI
software
3. Connect a user supplied external 6V supply
power to the ADS127L18 EVM
4. Connect the ADS127L18 EVM to the computer
with the included USB cable
5. Launch the ADS127L18 EVM GUI from the start
menu
6. Refer to the
ADS127L18 data sheet
7. Visit the
E2E forums
SBAU435 – FEBRUARY 2024
Submit Document Feedback
ti.com
for IC details
for support and questions
Copyright © 2024 Texas Instruments Incorporated
Features
Simultaneously measure eight channels
Data rate up to 512 kSPS (wideband filter)
Data rate up to 1.365 MSPS (low-latency filter)
AC performance with DC precision:
– 111.5dB dynamic range at 256 kSPS
– -120dB THD
– 0.9ppm of Full Scale INL
– 50nV/°C offset drift
– 0.6ppm/°C gain drift
Power-scalable speeds from 512 kSPS (28
mW/ch) to 50 kSPS (3.3 mW/ch)
Applications
Test and measurement:
Data acquisition (DAQ)
– Shock and vibration instruments
– Acoustics and dynamic strain gauges
Factory automation and
Condition monitoring
Aerospace and
defense:
– SONAR
Medical:
– Electroencephalogram (EEG)
Grid
infrastructure:
Power quality analyzer
ADS127L18EVM-PDK Evaluation Module
Description
control:
1

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Summary of Contents for Texas Instruments ADS127L18

  • Page 1 • Aerospace and defense: 4. Connect the ADS127L18 EVM to the computer with the included USB cable – SONAR 5. Launch the ADS127L18 EVM GUI from the start • Medical: menu – Electroencephalogram (EEG) 6. Refer to the ADS127L18 data sheet for IC details •...
  • Page 2: Kit Contents

    ® • The software suite includes graphical tools for data capture, histogram analysis, spectral analysis, and custom configuration of the ADS127L18. This suite also has a provision for exporting data to a text file for post-processing. External +6V, 500mA power...
  • Page 3: Specification

    ADS127L18 AVDD1 to GND DGND = GND Recommended absolute ratio range, external source, |AVSS/AVDD1| ≤ 1.2V/V ADS127L18 |AVSS/AVDD1| ratio to GND DGND = GND Recommended voltage range (R6 removed), external source 1.74V ≤ AVDD2 ≤ 5.5V ADS127L18 AVDD2 to AVSS -2.75V ≤...
  • Page 4 Single-ended 5Vpp, 0V o set Single-ended 5Vpp, 2.5V o s et ¡ Time (Secs) Time (Secs) CHxP CHxP Figure 2-1. Maximum input signal range (Vref = 2.5V) ADS127L18EVM-PDK Evaluation Module SBAU435 – FEBRUARY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 5: Power Requirements

    Ch4P Ch5P Ch6P Ch7P ADS127L18EVM A-to-Micro-B VCOM USB Cable ADS127L18EVM Ch3N Ch2N Ch1N Ch0N Ch3P Ch2P Ch1P Ch0P Signal Source Figure 2-2. Power Connections SBAU435 – FEBRUARY 2024 ADS127L18EVM-PDK Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 6 2.3 ADC Connections and Decoupling Figure 2-3 shows all connections to the ADS127L18 data converter (U1). Each power supply connection has a 10μF decoupling capacitor. Make sure these capacitors are physically close to the device and have a good connection to the GND plane. The supply connections also have a series 0Ω resistor. The purpose of this component is to facilitate current measurement for the ADC.
  • Page 7 C0G/NP0 2200pF TSW-104-07-G-S AVSS C0G/NP0 1µF 60312002114503 220pF 22.0 AINN0 AVSS AVSS 0.1% 1.00k 0.1% 1.00k 0.1% 22.0 0.1% Figure 2-4. ADC Input Amplifier SBAU435 – FEBRUARY 2024 ADS127L18EVM-PDK Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 8: Voltage Reference

    ADS127L18 through the 0Ω resistor R62. The REF6225 includes an integrated wide bandwidth buffer that is capable of driving the switched-capacitor input to the ADS127L18 without the need for an additional buffer. The REF6225 is sufficient to meet the ADS127L18 data sheet specifications for dynamic performance.
  • Page 9 Op Amp Stability Videos in TI Precision Labs. The default connection for the reference buffer input is the REF7040 reference output through resistor R76. To connect the reference buffer output to the ADS127L18 input, populate resistor R75 and remove resistors R62 and R63. REFERENCE BUFFER 1.00k 1.00k...
  • Page 10: Clock Tree

    JP1 is the 2-3 position (EVM CLK), which enables the local 32.768MHz oscillator (Y1) on the ADS127L18EVM board. This clock is routed to the clock input of the ADS127L18 to support all speed modes. Moving JP1 to the 1-2 position (EXT CLK) allows an external clock supplied on the SMA connector (J2). Use a CMOS square-wave signal with an amplitude equal to 1.8V (IOVDD) and a frequency within the specified range...
  • Page 11: Serial Interface

    2.9 Serial Interface Figure 2-9 shows the digital connections between the ADS127L18EVM and the PHI. The ADS127L18 ADC uses SPI serial communication in mode 1 (CPOL = 0, CPHA = 1) to configure the internal registers and a Frame-Sync Data Port for conversion data. Because the serial clock (SCLK) frequency and data clock (DCLK) frequency can be as fast as 32.768MHz, the ADS127L18EVM offers 10Ω...
  • Page 12: Power Supplies

    EVM controller (PHI) for EVM identification only. The EEPROM communicates with the PHI over an I2C bus and is not shared with the ADS127L18. This circuit is not required by the ADS127L18 for operation and is powered down when not used with the PHI.
  • Page 13 Hardware 2.12 Low Dropout Regulator (LDO) Figure 2-12 shows how the ADS127L18 AVDD, AVSS, and IOVDD supplies are generated. Power is provided by an external supply on either J7 or J6; refer to Section 2.11 Figure 2-11 for more details. AVDD and IOVDD are regulated to 5V and 1.8V, respectively, using low-noise TPS7A47 LDOs.
  • Page 14 3 Software 3.1 Software Description The ADS127L18EVM-PDK-GUI software suite includes graphical tools for data capture, full ADS127L18 register configuration, time domain analysis, histogram analysis, and spectral analysis. This suite also has a provision for exporting data to a text file for post-processing.
  • Page 15 Software Figure 3-1. Software Installation and Prompts (1) SBAU435 – FEBRUARY 2024 ADS127L18EVM-PDK Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 16 Software www.ti.com Figure 3-2. Software Installation and Prompts (2) ADS127L18EVM-PDK Evaluation Module SBAU435 – FEBRUARY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 17 Figure 4-1 after installing the software: 1. Physically connect P2 of the PHI to J1 of the ADS127L18 EVM. Install the included screws to provide a robust connection. 2. Connect an external +6V, 0.5A lab supply to J7 or connect an AC power adapter rated for 6V, 0.5A to J6 such as SMI18-5.9-V-P5 or equivalent.
  • Page 18 Buffered Vcm output voltage Optional 4.096V reference (use with external FPGA (used with external source) (not populated) development board) Figure 4-3. Optional EVM Connections ADS127L18EVM-PDK Evaluation Module SBAU435 – FEBRUARY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 19 This page can be accessed by selecting the Register Configurations under Pages on the left side of the GUI. Figure 4-4. EVM Register Configuration SBAU435 – FEBRUARY 2024 ADS127L18EVM-PDK Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 20 2.5V EVM configuration. Please refer to the ADS127L18 data sheet for more details on the function of these settings. Figure 4-5. ADC Configuration ADS127L18EVM-PDK Evaluation Module SBAU435 – FEBRUARY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 21: Clocking Configuration

    Updating the External Clock value also updates the calculated Data Rate. Please refer to the ADS127L18 data sheet for more details on the function of these settings. Figure 4-6. Clocking Configuration SBAU435 – FEBRUARY 2024 ADS127L18EVM-PDK Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 22 Please refer to the ADS127L18 data sheet for more details on the function of these settings. Figure 4-7. SPI and Data Port Configuration ADS127L18EVM-PDK Evaluation Module SBAU435 – FEBRUARY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 23: Filter Configuration

    8 channels, including both wideband filters and multiple SINC filter options. Please refer to the ADS127L18 data sheet for more details on the function of these settings. Figure 4-8. Filter Configuration SBAU435 – FEBRUARY 2024 ADS127L18EVM-PDK Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 24: Channel Configuration

    8 channels, including input configuration, input buffer enable, input range, and channel power-down. Please refer to the ADS127L18 data sheet for more details on the function of these settings. Figure 4-9. Channel Configuration ADS127L18EVM-PDK Evaluation Module SBAU435 – FEBRUARY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 25 Switching pages to any of the analysis tools described in the subsequent sections causes calculations to be performed on the same set of data. Figure 4-10. Time Domain Display SBAU435 – FEBRUARY 2024 ADS127L18EVM-PDK Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 26 Figure 4-11, is intended to evaluate the dynamic performance (SNR, THD, THD+N, SFDR, and Dynamic Range) of the ADS127L18 ADC through single-tone sinusoidal signal FFT analysis using the 7-term Blackman-Harris window setting. The FFT tool includes windowing options that are required to mitigate the effects of non-coherent sampling (this discussion is beyond the scope of this document).
  • Page 27 As shown Figure 4-12, the histogram corresponding to a dc input is displayed on clicking the Capture button. Figure 4-12. Histogram Display SBAU435 – FEBRUARY 2024 ADS127L18EVM-PDK Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 28 GP IO0 Thermal_Pad TS W-106-07-G-D ADS 127L18IRSHR S DO AVS S S DI S CLK TS W-104-07-G-D Figure 5-1. ADS127L18EVM ADC Interface and Reference Schematic ADS127L18EVM-PDK Evaluation Module SBAU435 – FEBRUARY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 29 C105 C106 C107 C108 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF Thermal_Pad TP S 7A4700RGWR Figure 5-2. ADS127L18EVM External Power Schematic SBAU435 – FEBRUARY 2024 ADS127L18EVM-PDK Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 30 REFP 0.1% 7.50 OPA211IDGKR 4.99k 1.00k 0.1% 0.033µF 0.1% 1µF 1.00k 47uF 1.00k REFN AVS S Figure 5-3. ADS127L18EVM Reference and VCOM Buffer Schematic ADS127L18EVM-PDK Evaluation Module SBAU435 – FEBRUARY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 31 R102 R103 AVS S AVS S 0.1% 1.00k 0.1% R104 1.00k 0.1% R105 22.0 0.1% Figure 5-4. ADS127L18EVM Input Channels 0 and 1 Schematic SBAU435 – FEBRUARY 2024 ADS127L18EVM-PDK Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 32 R128 R129 AVS S AVS S 0.1% 1.00k 0.1% R130 1.00k 0.1% R131 22.0 0.1% Figure 5-5. ADS127L18EVM Input Channels 2 and 3 Schematic ADS127L18EVM-PDK Evaluation Module SBAU435 – FEBRUARY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 33 R154 R155 AVS S AVS S 0.1% 1.00k 0.1% R156 1.00k 0.1% R157 22.0 0.1% Figure 5-6. ADS127L18EVM Input Channels 4 and 5 Schematic SBAU435 – FEBRUARY 2024 ADS127L18EVM-PDK Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 34 R180 R181 AVS S AVS S 0.1% 1.00k 0.1% R182 1.00k 0.1% R183 22.0 0.1% Figure 5-7. ADS127L18EVM Input Channels 6 and 7 Schematic ADS127L18EVM-PDK Evaluation Module SBAU435 – FEBRUARY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 35: Pcb Layouts

    Hardware Design Files 5.2 PCB Layouts Figure 5-8. PCB Layout for the ADS127L18EVM (Top View) Figure 5-9. PCB Layout for the ADS127L18EVM (Bottom View) SBAU435 – FEBRUARY 2024 ADS127L18EVM-PDK Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 36 Hardware Design Files www.ti.com Figure 5-10. PCB Layout (internal AVSS/GND plane 1) for the ADS127L18EVM Figure 5-11. PCB Layout (internal AVSS/GND plane 2) for the ADS127L18EVM ADS127L18EVM-PDK Evaluation Module SBAU435 – FEBRUARY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 37 C38, C41, C44, C47, C50, C53, C56, C59, CAP, CERM, 220pF, 50V, +/- 1%, C0G/NP0, 220pF 0603 06035A221FAT2A C62, C65, C68, C71, 0603 C74, C77, C80, C83 SBAU435 – FEBRUARY 2024 ADS127L18EVM-PDK Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 38 R25, R26, R27, R28, RES, 10.0, 1%, 0.25 W, AEC-Q200 Grade 0, 0603 CRCW060310R0FKEAHP Vishay-Dale R29, R30, R32, R33, 0603 R34, R35, R36, R37, R38, R39 ADS127L18EVM-PDK Evaluation Module SBAU435 – FEBRUARY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 39 RES, 1.00 k, 0.1%, 0.1 W, AEC-Q200 Grade 0, 1.00k 0603 ERA3AEB102V Panasonic R133, R135, R142, 0603 R143, R146, R148, R155, R156, R159, R161, R168, R169, R172, R174, R181, R182 SBAU435 – FEBRUARY 2024 ADS127L18EVM-PDK Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 40 Adjustable -1.18V to -33V Output, -3V to -36V Input, with Ultra-Low Noise, 8-pin MSOP DGN0008D TPS7A3001DGNR Texas Instruments (DGN), -40 to 125 degC, Green (RoHS & no Sb/Br) ADS127L18EVM-PDK Evaluation Module SBAU435 – FEBRUARY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 41 Low Noise, Precision, 150MHz, Fully DGK0008A THS4551IDGKR Texas Instruments U14, U15, U16, U17 Differential Amplifier, DGK0008A (VSSOP-8) High-Performance BAW Oscillator 25.6MHz, VSON4 LMK6CE02560DDLFR Texas Instruments 1.8V LVCMOS Output SBAU435 – FEBRUARY 2024 ADS127L18EVM-PDK Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 42: Additional Information

    Microsoft Corporation. All trademarks are the property of their respective owners. 7 Related Documentation 7.1 Supplemental Content Table 7-1 shows the related documentation from Texas Instruments. Table 7-1. Related Documentation Document Literature Number ADS127L18 product data sheet...
  • Page 43 STANDARD TERMS FOR EVALUATION MODULES Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms set forth herein.
  • Page 44 www.ti.com Regulatory Notices: 3.1 United States 3.1.1 Notice applicable to EVMs not FCC-Approved: FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kit to determine whether to incorporate such items in a finished product and software developers to write software applications for use with the end product.
  • Page 45 www.ti.com Concernant les EVMs avec antennes détachables Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à...
  • Page 46 www.ti.com EVM Use Restrictions and Warnings: 4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS. 4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling or using the EVM, including without limitation any warning or restriction notices.
  • Page 47 Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief in any United States or foreign court. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated...
  • Page 48 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2024, Texas Instruments Incorporated...

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