Xilinx SP623 Getting Started Manual page 21

3.
X-Ref Target - Figure 21
Open Cable Button
4.
X-Ref Target - Figure 22
5.
X-Ref Target - Figure 23
Starting the Clock Module
The IBERT demonstration design uses a ChipScope VIO core to control the clocks on the
SuperClock-2 module. The SuperClock-2 module features two clock-source components:
SP623 IBERT Getting Started Guide
UG752 (v1.0.1) January 26, 2011
When the new project window opens, click the Open Cable button
Figure 21: Open Cable Button
When the dialog box opens asking to set up the core with settings from the current
project, click Yes (Figure
Figure 22: Core Settings Dialog Box
When the project panel opens, verify the JTAG chain shows the devices listed in
Figure 23.
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22).
Figure 23: Project Panel
Procedure
(Figure 21).
UG752_21_052610
UG752_22_052610
UG752_23_052610
21