Flashfreeze_Sb_0 Module; Figure 22 Top-Level Dsp Design - Microchip Technology Microsemi Hello FPGA Libero Design User Manual

DSP (FIR) Filter Demo Design
Figure 22 shows the top-level DSP FIR_LCD_FF demo design in Libero.
Figure 22 • Top-Level DSP Design
The Top module contains the following modules:
•

FlashFreeze_SB_0 Module

• FIR_FILTER_0 Module
• LCD_DISPLAY_0 Module
5.1 FlashFreeze_SB_0 Module
The FlashFreeze_SB_MSS module configures the Microcontroller Subsystem (MSS).
• The SPI peripheral in the MSS is used to store the images in SPI flash and to read the images from
SPI flash.
• The UART peripheral in MSS is used to communicate with the GUI on host PC through PIC32
microcontroller.
• MSS is the APB master which is connected to the APB slave (apb3_if) module to initialize LCD
registers during startup.
• The Flash_FREEZE module provides the feature of low power FF mode to the FPGA. The
FF_Entry_SW signal provides the hardware interrupt for FF to MSS.
When a Flash*Freeze user interrupt is received by the MSS, the instruction related to Flash*Freeze is
executed and the FPGA goes into the Flash*Freeze mode. The MSS is in an infinite loop when the FPGA
fabric is in the Flash*Freeze mode.
Figure 23 shows the blocks inside the FlashFreeze_SB_0 module.
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