Microchip Technology Microsemi Hello FPGA Libero Design Manuals

Manuals and User Guides for Microchip Technology Microsemi Hello FPGA Libero Design. We have 1 Microchip Technology Microsemi Hello FPGA Libero Design manual available for free PDF download: User Manual

Microchip Technology Microsemi Hello FPGA Libero Design User Manual

Microchip Technology Microsemi Hello FPGA Libero Design User Manual (26 pages)

Brand: Microchip Technology | Category: Microcontrollers | Size: 2 MB

Table of Contents

Table of Contents
3
1 Revision History

6
- Revision 1.0
  6
2 Hello FPGA

7
- Figure 1 Hello FPGA Kit
  8
- Figure 2 LCD and Camera Sensor Boards
  8
3 Video Demo Design

9
- Line_Write_Read Module
  9
  - Figure 17 Flashfreeze_Sb
    9
  - Figure 3 Top-Level Hardware Implementation (Video Demo)
    9
  - Figure 4 Line_Write_Read SD
    10
  - Image Enhancement
    10
  - Lcd_Fsm
    10
  - Write_Lsram_0
    10
- Flashfreeze_Sb Module
  11
  - CCC Ip
    12
  - Flash_Freeze Ip
    12
  - Figure 6 CCC IP Configuration
    12
  - Mss Ip
    13
  - Figure 8 MSS Component Configuration
    13
- Uart_Interface
  14
  - Coreuart_C0
    14
  - Figure 9 Uart_Interface SD
    14
  - Figure 10 Coreuart C0 Configuration
    14
- Apb3_If (APB Slave)
  15
- Mux_2_1
  15
- Ff_Ext
  15
- Figure 11 Apb3_If
  15
- Figure 12 MUX_2_1
  15
- Figure 13 FF_EXT Module
  15
- Ff_Generator
  16
- Osc_C0 Ip
  16
- Figure 14 Ff_Generator Module
  16
- Figure 15 OSC_C0 IP Core Configuration
  16
- Resource Utilization
  17
4 Digit Recognition (AI) Demo Design

18
- Figure 16 Top-Level Hardware Implementation (AI Digit Recognition)
  18
  - Flashfreeze Smartdesign
    19
  - Apb3_If (APB Slave)
    20
  - Figure 18 APB Slave Module Configuration
    20
  - Line_Write_Read Smartdesign
    21
  - Top Cnn
    21
  - Figure 19 Line_Write_Read SD
    21
  - Figure 20 Implemented Smartdesign Block Diagram
    21
  - Resource Utilization
    22
5 DSP (FIR) Filter Demo Design

23
- Figure 21 DSP FIR Filter Block Diagram
  23
  - Flashfreeze_Sb_0 Module
    24
  - Figure 22 Top-Level DSP Design
    24
  - FIR_FILTER_0 Module
    25
  - Figure 23 Flashfreeze_Sb_0
    25
  - Figure 24 FIR_FILTER Module
    25
  - LCD_DISPLAY_0 Module
    26
  - Resource Utilization
    26
  - Figure 25 LCD_DISPLAY_0 Module
    26

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