Ccc Ip; Flash_Freeze Ip; Figure 6 Ccc Ip Configuration - Microchip Technology Microsemi Hello FPGA Libero Design User Manual

Video Demo Design
3.2.1

CCC IP

CCC IP is available in Libero SoC -> Clock and Management IP catalog. CCC IP acquires the 25/50
MHZ clock from the on-chip oscillator IP and generates the GL0 clock of 100 MHz and GL1 of 24 MHz
clock. All the modules inside FPGA works on GL0 clock. The following figure shows the configuration of
the CCC IP.
Figure 6 • CCC IP Configuration
3.2.2

FLASH_FREEZE IP

FLASH FREEZE IP is available in Libero SoC -> Catalog. SmartFusion2 SoC FPGA devices provide an
ultra-low static power solution through Flash*Freeze technology. Flash*Freeze mode entry retains all the
Static Random Access Memory (SRAM) and registers information. Flash*Freeze mode exit achieves
rapid recovery to active mode (approximately 13 µs). The following figure shows the FLASH FREEZE IP.
Figure 7 • Flash_Freeze IP
Microsemi Proprietary UG0891 Revision 1.0 7