Line_Write_Read Smartdesign; Top Cnn; Figure 19 Line_Write_Read Sd; Figure 20 Implemented Smartdesign Block Diagram - Microchip Technology Microsemi Hello FPGA Libero Design User Manual

Digit Recognition (AI) Demo Design
4.3

Line_write_read SmartDesign

Figure 19 • Line_write_read SD
Line write read SmartDesign displays three images on the LCD:
1. Image from camera.
2. Image from camera in the scalable of size 28x28 at top left corner of LCD.
3. Recognized digit of size 80x80 at left bottom corner.
The FPGA receives video from the camera with a resolution of 640x480 at 30fps. WRITE_LSRAM
perform scaling of the input video to the 480x320 video format of LCD and write scalable data on the
ramDualPort_0. Similarly, WRITE_LSRAM_SCALE performs scaling of video from the camera to the
28x28, which is the resolution required by CNN. The actual scaled image passed to the CNN is displayed
through the 28x28 scaled image. Recognized digit OSD data is provided by the MSS through the APB
slave of size 80x80, WRITE_LSRAM_DIGIT module saves digit OSD data into the ramDualPort_2.
Init_done signal from the MSS indicates the LCD is initialized and MSS gives control of LCD to the
LCD_FSM module. LCD_FSM module reads data from all these RAMs and displays it on the LCD
according to the interface protocol.
4.4

TOP CNN

Figure 20 • Implemented SmartDesign block diagram
The above figure shows the block diagram of the implemented SmartDesign. The network implemented
in the demo contains 4 convolution layers, a max pool layer, and a fully connected layer. The network is
trained from the standard MNIST handwritten digit database which contains the digits in 28x28 resolution
images. The CNN can detect a single digit in the 28x28 image when the aspect ratio of the digit is
approximately equal to the aspect ratio of the trained image data set. The network is built for only 10
classes for digits from 0 to 9 and does not use a class that shows no digit. Hence even though the
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