Dsp (Fir) Filter Demo Design; Figure 21 Dsp Fir Filter Block Diagram - Microchip Technology Microsemi Hello FPGA Libero Design User Manual

DSP (FIR) Filter Demo Design

5 DSP (FIR) Filter Demo Design
In this DSP FIR filter demo design, the FIR filter is implemented in the fabric for Low pass, High pass,
Band pass, and Band reject filtering operations. The host interface is implemented in the fabric to
communicate with the host PC. A user friendly graphical user interface (GUI) generates the filter
coefficients, input signals (Pass-band frequency + Stop-band frequency) and also plots the input/output
waveforms and the required spectrum. Microchip CoreFIR filter IP is used to suppress the unwanted
frequency components, and generate the output signals to verify the filtering operation.
Figure 21 • DSP FIR Filter Block Diagram
SPI Flash
The demo design also implements an LCD display application, which displays images stored in SPI flash
on an ILI9488 LCD display. The MSS UART is used to read and write the image data into the SPI flash.
For this demo, the SPI flash is preloaded with Microchip logo and a Hello FPGA board image.
Both the applications use UART communication to interface with PIC32 micro-controller which is
interfaced with host PC for GUI, due to which a UART_SELECTION module is used to switch between
fabric UART and the MSS UART. The Fabric UART is used for DSP FIR application and the MSS UART
is used for LCD display application.
SPI MSS
FIC
APB3 Slave LCD_FSM
Coefficient Buffer
Control FIR Input Data Buffer
Logic
FIR Output Data Buffer
Microsemi Proprietary UG0891 Revision 1.0
MM UART
UART
GUI
Selection
MUX LCD
LCD_DISPLAY
CoreFIR
FIR_FILTER
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