Fir_Filter_0 Module; Figure 23 Flashfreeze_Sb_0; Figure 24 Fir_Filter Module - Microchip Technology Microsemi Hello FPGA Libero Design User Manual

DSP (FIR) Filter Demo Design
Figure 23 • FlashFreeze_SB_0
5.2

FIR_FILTER_0 Module

The FIR_FILTER_0 module implements the user logic in the fabric. This module implements the
following finite-state machines:
• Data Handling: Implements and controls operations like loading the filter input data to the
corresponding input data buffer and loading filter coefficients to the corresponding coefficient
memory buffers.
• Filter Control: Controls the FIR filter operation. Loads the filtered data to the corresponding output
buffer.
• CoreFIR IP: The Core FIR IP is used in Re-loadable coefficient mode to support Low pass, High
pass, Band pass, and Band reject filters.
• TPSRAM IP: The TPSRAM IP is used to implement Filter coefficient buffer, Input signal data buffer,
Output signal buffer.
Figure 24 figure shows the blocks inside the FIR_FILTER_0 module.
Figure 24 • FIR_FILTER Module
Microsemi Proprietary UG0891 Revision 1.0 20