Uart_Interface; Coreuart_C0; Figure 9 Uart_Interface Sd; Figure 10 Coreuart C0 Configuration - Microchip Technology Microsemi Hello FPGA Libero Design User Manual

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Video Demo Design

3.3

UART_interface

Figure 9 •

UART_interface SD

UART_interface SmartDesign performs the task of communication between the SmartFusion2 FPGA

and the PC with PIC microcontroller as a bridge. Based on the data from Hello_FPGA GUI, receive_data

module generates the address and the data. Addr_decoder module generates the values of brightness,

contrast, and color and provides it to the Image_enchancement module.

3.3.1

COREUART IP is available in the Libero SoC peripheral IP catalog. BAUD rate of UART is 230400,

based on the operating clock frequency, BAUD_VAL, and BAUD_VAL_FRACTION values. The following

figure shows the CoreUART configuration.

Figure 10 • CoreUART C0 Configuration

Microsemi Proprietary UG0891 Revision 1.0

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