Memory Circuit - Tektronix 1S1 Instruction Manual

Memory Circuit

The memory circuit is an operational amplifier using
capacitors for both the input and feedback elements. The
input capacitor is C76 at the output of the ac amplifier,
and the feedback capacitor is the parallel combination of
C135 and C136.
The error-correction signal from the ac amplifier is applied
through the memory gate to the grid of V44B. The feedback
action of the memory circuit places a charge on C135 and
C136 equal to that applied to the input capacitor (C76).
The memory gate then disconnects before the pulse from the
ac amplifier has ended and the charge is left on C135
and C136.
Capacitor C135 adjusts the gain of the memory circuit to
approximately 2.6, set by the ratio of C135 and C136 to
C76, which adjusts the sampling loop gain to 1. A high-
gain capability is needed to keep the voltage excursions at
the grid of V44B very small compared to the memory output.
(Open loop gain of the circuit is about 1500.) Any tendency
for the grid level to change, as a result of input signal
change, is amplified and returned as negative feedback
through C135 and C136 to hold the grid level nearly
stationary.
Between samples, the input capacitor is discharged and
the ac amplifier output returns to a quiescent level. When
the next sampled pulse is received, if there is a change at
the input, the memory capacitor will receive a new signal
Fig. 3-5. Block diagram of the Memory circuit.
Circuit Description – Type 1S1
and will add or subtract the new signal from the residual
charge, depending on whether the new level is above or
below the previous one. Since grid current in V44B is very
low and total leakage from the memory capacitor is very
small, there is essentially no change in the memory output
level between samples if there is no change at the input.
Memory drift (dot slash) that may occur at a sampling rate
below approximately 50 samples/sec is caused by a small
amount of leakage current.
DC Offset
The dc offset circuit consists of emitter follower Q153
which introduces dc shift into the sampling feedback loop.
This transistor serves as a low-impedance source connected
to the feedback loop between R145K and R145L. Front-
panel DC OFFSET control R159 causes a -17-volt to +17-
volt swing at the base of Q153 as the control is rotated from
one end to the other. The emitter swing, following the base,
causes a swing of ±1 volt in the feedback loop and a
voltage swing of ±10 volts at the OFFSET OUTPUT jack
Current through the feedback attenuator remains constant,
regardless of the dc voltage level inserted by Q153.
Feedback Loop
Feedback from the memory output to the sampling gate
bridge makes up for the 30% efficiency of the sampling gate.
Since the memory output level determines the level of each
3-7