Circuit Analysis; Vertical System; Cycle Of Operation - Tektronix 1S1 Instruction Manual

Circuit Description – Type 1S1
moves down one step each time, the fast ramp has to run
slightly farther each time before a comparison pulse is pro-
duced. In this way the sampling event is delayed by suc-
cessively longer intervals and the samples are taken suc-
cessively later along the waveform with respect to the
triggering point. Each time a sample is taken, the crt is
blanked momentarily while the dot position on the crt moves
horizontally by one increment. Since the vertical channel is
an error-sensing circuit, the vertical position of the dot
changes only if the input voltage level changes between
samples.
Fig. 3-2 illustrates the development of an equivalent-time
display from a repetitive square-wave signal. Note that the
sampling operation is triggered each time at the same point
on the triggering waveform, but that the sample is taken
progressively later on the waveform, due to the longer delay
between the triggering event and the sampling event. No
two samples are taken from the same cycle of the input
waveform.

CIRCUIT ANALYSIS

The Type 1S1 circuitry consists of a horizontal channel
and a vertical channel, each of which may be subdivided
into several basic circuits. The fold-out block diagram at the
rear of this manual shows each basic circuit as a block and
indicates the functional relationships existing between the
circuits. Refer to this block diagram for the basic operation
of the system and refer to the detailed block diagrams in
the text and the particular schematic diagrams at the rear
of the manual for the detailed analysis of each circuit. The
following descriptions are arranged in essentially the same
sequence as the schematic diagrams.
3-2
Fig.3-2. Formation of crt display by equivalent-time sampling process.

VERTICAL SYSTEM

The vertical system of the Type 1S1 uses a balanced-bridge
error- correction type of sampling operation, providing vertical
deflection voltages for the display oscilloscope. It has an
internal trigger takeoff circuit which may be used to start the
trigger circuit operation. The input signal is delayed ap-
proximately 45 nsec after the trigger takeoff to allow the
trigger circuit to begin the sampling cycle before the signal
has reached the sampling gate diode bridge. A zero-order-
hold memory is used to remember the value of the previous
sample.
The sampling repetition rate ranges from approximately 50
cps to about 80 kc, depending on the repetition rate of the
triggering signal and the recovery time of the trigger holdoff
circuit. If a rate slower than about 50 cps is used, the memory
output may drift, and memory "dot slash" may be seen. The
maximum rate of 80 kc allows sufficient time for the sampling
unit to pass a sample and recover before another sample is
taken. Above 80 kc, countdown of the triggering signal occurs
automatically.

Cycle of Operation

The vertical input signal is applied through a 50-ohm
coaxial connector and passes through the trigger takeoff
and a 50-ohm coaxial delay cable to the sampling gate.
The trigger takeoff transformer takes off a small portion of
the input signal and sends it to the trigger circuit to be
used for starting the operation of the sampling cycle.
After being triggered, the horizontal circuitry sends a
sampling-drive pulse to the blocking oscillator in the vertical
system. The blocking oscillator then pulses the snap-off
circuit with a fast pulse and the memory gate driver with a
slower pulse. Short push pull pulses from the snap-off