Tektronix 1S1 Instruction Manual page 43

Circuit Description – Type 1S1
Sampler Preamplifier
The sampled pulse from the sampling gate is sent through
R36 to the grid of V44A which amplifies the signal and
applies it to the base of Q54. The signal is again amplified
by Q54 and sent through C56 and the SMOOTHING con-
trol to the error-correction attenuator.
The feedback loop from the collector of Q54 to the
cathode of V44A sets the output amplitude of the sampler
preamplifier and also bootstraps V44A to keep the grid
impedance relatively high. Gain of the circuit is approxi
mately 13, set primarily by R52 and R39. The duration of
the output pulse is stretched to about 400nsec by the ca-
pacitance at the grid of V44A and by the time constant of
R52-L52.
Error-Correction Attenuator
The amount of attenuation produced by the error-correc-
tion attenuator, R58-R60, is selected by the mVOLTS/CM
switch (SW60) to maintain a gain of one in the sampling
feedback loop while the memory output amplitude is
changed with the feedback attenuator.
The SMOOTHING control (R56) is part of the voltage
divider at the input of the error-correction attenuator; thus,
the SMOOTHING control can adjust the error signal ampli-
tude across the divider to change the gain of the sampling
feedback loop. This does not affect the vertical gain of
the display, since it is within the sampling loop, but does
change the ability of the sampling loop to follow the
changes of the input signal. The loop is set for correct
response (unity loop gain) when the SMOOTHING control
is set to NORM (clockwise) position. When the control is then
turned counterclockwise,
and the feedback voltage to the sampler preamplifier input
cannot provide full correction for the 30% sampling ef-
ficiency. Decreasing the loop gain permits a reduction of
system noise amplification when high input sensitivities are
used but also may reduce the apparent transient response
of the system if the display dot density is too low.
AC Amplifier
The ac amplifier is made up of an amplifier and an out-
put emitter follower with dc-coupled negative feedback.
The error-correction pulse from the attenuator is applied
through R62 to the base of Q64. The amplified and inverted
signal at the collector of Q64 is then connected through
emitter follower Q74 to the output of the circuit. Amplifica-
tion of the stage is about 30. The error-correction signal is
then applied to C76 at the memory gate input to be used
for charging the memory capacitor.
Memory Gate Driver
Diodes D90 and D92 at the input to the memory gate
driver are forward biased and conducting between sampling
pulses. Current division between the diodes is adjusted by
R95, the MEMORY GATE WIDTH control, which also sets
the voltage at the base of Q94 slightly positive and holds
the transistor in cutoff. A voltage of approximately -19 volts on
the collector of Q94,
gate circuit, sets the transistor so that it will saturate easily.
3-6
the loop gain is decreased
received through the memory
As D90 is momentarily reverse biased by the negative-go-
ing pulse from the blocking oscillator, current which had
been passing through D90 is switched to D92. This causes
Q94 to saturate quickly, producing the positive-going mem-
ory gate driver pulse at the collector of Q94. This positive-
going gate pulse is sent to T110 in the memory,gate circuit
to turn on the gate, and to the base of the interdot blank-
ing amplifier, Q294.
When the differentiated pulse from the blocking oscillator
ends, D90 becomes forward biased again, decreasing cur-
rent through D92. As soon as the charge in the base-to-
emitter circuit of Q94 has been depleted, the transistor
turns off, ending the memory gate driver pulse. The width
of the pulse is adjusted for best performance of the sampling
loop by the MEMORY GATE WIDTH control which deter-
mines the amount of charge stored in Q94 during the time
that D90 is reverse biased. When R95 is set correctly, the
duration of the memory gate pulse is about 350nsec.
Interdot Blanking Amplifier
The base of Q294 is quiescently set at -19 volts by the
voltage received through T110 in the memory gate, keeping
Q294 turned off. The positive-going pulse applied to the
base turns on the transistor, sending a negative-going output
pulse through R297 and terminal 8 of the interconnecting
plug to the chopped blanking circuit in the oscilloscope.
Though Q294 is turned on only for the duration of the
memory gate driver pulse (approximately 350 nsec), the time
duration of the interdot blanking is extended to at least
1.5 µsec by the RC time constant in the oscilloscope chopped
blanking circuit.
MEMORY
On the memory schematic diagram are shown the memory
gate, the memory, the feedback attenuator, the dc offset
emitter follower and the vertical output and positioning
cathode followers. Fig. 3-5 is a detailed block diagram of
the memory.
Memory Gate
The memory gate consists of diodes D110 and D112
which are pulsed into conduction by the memory gate driver
through T110. The purpose of the gate is to allow the
sampled error-correction signal to pass through to the
memory circuit, but prevent the feedback signal that is
regenerated through the amplifiers from being applied to
the memory as a new error-correction signal. The memory
gate is non-conducting by the time the signal is returned
through the loop.
The gate diodes are normally reverse biased, with about
3 volts reverse bias set by zener diode D101. When a pulse
is received from the memory gate driver, a voltage is
developed across each winding of T110, forward biasing
the gate diodes. The signal then passes from C76 at the
output of the ac amplifier to the input of the memory circuit.
The dc level at the memory gate input is set by the MEM-
ORY BAL adjustment, R110, so that with no error-correction
signal present at the input, there will be no change in the
memory output level. Capacitor C101 assures that both
sides of the zener diode follow the signal equally well.