The following figure shows an example of an output sequence for the case that you set
SW_ENABLE while digital input DIn.0 is set.
Figure 4-6
If you set SW_ENABLE while digital input DIn.0 is set, the first (falling) edge of DIn.0 is
ignored.
Technology Module TM Pulse 2x24V (6ES7138‑6DB00‑0BB1)
Manual, 05/2019, A5E35061186-AB
Example 2 of an output sequence
Configuring/address space
4.4 On/Off delay mode
81