Status Reporting Data Structures
The following figure shows how the status register bits are masked and logically
OR'ed to generate service requests (SRQ) on particular events.
+
OR
Keysight InfiniiVision M9241/42/43A PXIe Oscilloscopes SCPI Programmer's Guide
PLL
Locked
15
14
13
12
11
10
Ext Trig
Chan4
Fault
Fault
15
14
13
12
11
10
Auto
Pass
Mask
15
14
13
12
11
10
OR
OR
+
+
To bits in Operation Status Condition Register:
HWE
OVLR
MTE
9
8
7
6
5
4
3
Chan3
Chan2
Chan1
Ext Trig
Chan4
Fault
Fault
Fault
OVL
OVL
9
8
7
6
5
4
3
Started
9
8
7
6
5
4
Status Reporting
:HWERegister:CONDition?
Hardware Event Condition Register
0
:HWERegister[:EVENt]?
Hardware Event Event Register
2
1
0
:HWEenable
:HWEenable?
Hardware Event Enable (MASK) Register
:OVLR?
Chan3
Chan2
Chan1
OVL
OVL
OVL
Overload Event Register
2
1
0
:OVL
:OVL?
Overload Event Enable (Mask) Register
Com-
:MTERegister[:EVENt]?
Fail
Mask Test Event Event Register
plete
3
2
1
0
:MTEenable
:MTEenable?
Mask Test Event Enable (MASK) Register
37
1303
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