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VCC_3v3
R2
R2
20K
20K
VCC_3v3
J1
J1
1
2
3
4
5
6
1
2
SW1
SW1
C1
C1
KSR211GLFS
KSR211GLFS
RESET
0.1uF
0.1uF
MII_RXD[3:0]
R6
R6
499
499
C3
C3
0.056uF
0.056uF
VCC_3v3
C6
C6
C7
C7
C8
C8
C9
C9
C10
C10
C11
C11
C12
C12
C13
C13
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
RTC_VCC
UM024401-0412
D[7:0]
U1
U1
D0
L2
D0
K3
D1
D1
D2
J4
D2
D3
M3
D3
D4
L3
D4
VCC_3v3
D5
H5
D5
D6
L4
D6
M4
D7
R1
R1
D7
20K
20K
L6
VCC_3v3
WAIT
R3
R3
R4
R4
R25
R25
20K
20K
M7
J21
J21
BUSREQ
10K
10K
10K
10K
J6
1
NMI
H7
TMS
ZCL
L9
TCK
ZDA
K9
TDI
L10
TRSTN
SYS_RST-
K6
RESET
A2
WP
D8
MII_CRS
MII_CRS
A7
MII_COL
MII_COL
D6
MII_RXER
MII_RXER
A4
MII_RXDV
MII_RXDV
MII_RXD3
C4
MII_RXD3
MII_RXD2
D5
MII_RXD2
B4
MII_RXD1
MII_RXD1
E6
MII_RXD0
MII_RXD0
C5
MII_RXCLK
MII_RXCLK
C6
MII_TXCLK
MII_TXCLK
J10
FILT_IN
H11
XIN
C2
C2
Y1
Y1
H12
XOUT
220pF
220pF
H10
5.000MHZ
5.000MHZ
VCC_3v3
PLL_VDD
R9
R9
G7
PLL_VSS
C4
C4
A5
100K
100K
VDD1
C5
C5
B8
VDD2
C1
22pF
22pF
VDD3
22pF
22pF
C10
VDD4
E2
VDD5
E11
VDD6
G2
VDD7
H9
VDD8
J2
C14
C14
C15
C15
C16
C16
C17
C17
C18
C18
VDD9
J11
VDD10
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
K4
VDD11
K7
VDD12
M1
VDD13
B5
VSS1
B12
VSS2
C2
VSS3
C8
VSS4
D9
VSS5
E3
J26
J26
VSS6
F9
VSS7
G3
1
VSS8
G6
2
VSS9
G12
VSS10
H4
VSS11
HDR/PIN 1x2
HDR/PIN 1x2
H6
VSS12
J12
VSS13
K8
VSS14
M2
VSS15
M11
VSS16
J7
RTC_VDD
L8
RTC_XOUT
Y2
Y2
M8
RTC_XIN
C19
C19
32.768KHZ
32.768KHZ
C20
C20
18pF
18pF
18pF
18pF
eZ80F91_BGA
eZ80F91_BGA
Figure 12. Schematic Diagram #4 of 4: eZ80F91 MCU
A[22:0]
A1
A0
A0
B1
A1
A1
B2
A2
A2
C3
A3
A3
D4
A4
A4
E5
A5
A5
D2
A6
A6
D1
A7
A7
D3
A8
A8
F6
A9
A9
E1
A10
A10
E4
A11
A11
F1
A12
A12
F2
A13
A13
F3
A14
A14
F4
A15
A15
G1
A16
A16
F5
A17
A17
H1
A18
A18
H2
A19
A19
G4
A20
A20
H3
A21
A21
J1
A22
A22
G5
A23
MII_TXD[3:0]
B7
MII_TXD3
MII_TXD3
C7
MII_TXD2
MII_TXD2
D7
MII_TXD1
MII_TXD1
A6
MII_TXD0
MII_TXD0
B6
MII_TXEN
E7
MII_TXER
A3
R5
R5
33.2
33.2
MII_MDC
B3
MII_MDIO
MII_MDIO
M5
IORQ
L5
MRQ
K5
RD
RD-
J5
WR
WR-
L7
BUSACK
J3
CS0
FLASH_CS-
K1
L_SRAM_CS-
CS1
K2
CS2
U_SRAM_CS-
L1
CS3
A11
SCL
A12
SDA
A8
PA7
PA7_PWM3
F7
PA6
PA6_PWM2_EC1
C9
PA5
PA5_PWM1_TOUT1
A9
PA4
PA4_PWM0_TOUT0
B9
PA3
PA3_PWM3_OC3
E8
PA2
PA2_PWM2_OC2
B10
PA1
PA1_PWM1_OC1
A10
PA0
PA0_PWM0_OC0
C11
PB7
PB7_MOSI
C12
PB6
PB6_MISO
D10
PB5
PB5_ICB3
E9
PB4
PB4_ICA2
D11
PB3
PB3_SCK
F8
PB2
PB2_SS
D12
PB1
PB1_IC1
E10
PB0
PB0_IC0_EC0
E12
PC7
PC7_RI1
G8
PC6
PC6_DCD1
F10
PC5
PC5_DSR1
F11
PC4
PC3_J
PC4_DTR1
F12
PC3
PC3_CTS1
G9
PC2
PC1_J
PC2_RTS1
G10
PC1
PC1_RXD1
G11
PC0
PC0_TXD1
H8
PD7
PD7_RI0
K11
PD6
PD6_DCD0
K12
PD5
PD5_DSR0
J9
PD4
PD4_DTR0
K10
PD3
PD3_CTS0
L11
PD2
PD2_RTS0
L12
PD1
PD1_RXD0_IRRXD
M12
PD0
PD0_TXD0_IRTXD
M9
HALT_SLP
B11
R10
R10
33.2
33.2
PHI
1
M6
J19
J19
INSTRD
M10
Place resistor near CPU
TDO
J8
TRIGOUT
eZ80AcclaimPlus! Development Kit
RD-
J2
J2
MII_TXEN
1
MII_TXER
WR-
J3
J3
MII_MDC
1
FLASH_CS-
J4
J4
1
VCC_3v3
L_SRAM_CS-
J5
J5
1
U_SRAM_CS-
J6
J6
1
R7
R7
R8
R8
4.99K
4.99K
4.99K
4.99K
J7
J7
1
1
J8
J8
J10
J10
1
J9
J9
1
2
3
4
5
6
7
8
PC3_J
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PC2
51
52
PC0
53
54
PD0
55
56
57
58
59
60
PD1_J
Z i l o g C o n f i d e n t i a l A l l R i g h t s R e s e r v e d
Z i l o g C o n f i d e n t i a l A l l R i g h t s R e s e r v e d
Z i l o g C o n f i d e n t i a l A l l R i g h t s R e s e r v e d
61
62
63
64
Z i l o g
Z i l o g
Z i l o g
HDR/PIN 2x32
HDR/PIN 2x32
1590 Buckeye Drive
1590 Buckeye Drive
1590 Buckeye Drive
Milpitas, CA 95035
Milpitas, CA 95035
Milpitas, CA 95035
408-513-1500
408-513-1500
408-513-1500
Website: www.zilog.com
Website: www.zilog.com
Website: www.zilog.com
Title
Title
Title
eZ80F91 Development Board
eZ80F91 Development Board
eZ80F91 Development Board
Page
Page
Page
F91
F91
F91
Size
Size
Size
Document Number
Document Number
Document Number
B
B
B
User Manual
21
PB0
MII_RST-
J23
J23
CTS1-
J24
J24
PC1_J
RXD1
J25
J25
PD1_J
RXD0
RTS1-
TXD1
TXD0
96C1322-001G
96C1322-001G
96C1322-001G
Schematic Diagrams
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