Data Reception - Atmel AVR AT90S4434 Preliminary

AT90S/LS4434 and AT90S/LS8535
the next character. At the same time as the data is transferred from UDR to the 10(11)-bit shift register, bit 0 of the shift reg-
ister is cleared (start bit) and bit 9 or 10 is set (stop bit). If 9-bit data word is selected (the CHR9 bit in the UART Control
Register, UCR is set), the TXB8 bit in UCR is transferred to bit 9 in the Transmit shift register.
On the baud rate clock following the transfer operation to the shift register, the start bit is shifted out on the TXD pin. Then
follows the data, LSB first. When the stop bit has been shifted out, the shift register is loaded if any new data has been writ-
ten to the UDR during the transmission. During loading, UDRE is set. If there is no new data in the UDR register to send
when the stop bit is shifted out, the UDRE flag will remain set until UDR is written again. When no new data has been
written and the stop bit has been present on TXD for one bit length, the TX Complete flag (TXC) in USR is set.
The TXEN bit in UCR enables the UART Transmitter when set (one). When this bit is cleared (zero), the PD1 pin can be
used for general I/O. When TXEN is set, the UART Transmitter will be connected to PD1, which is forced to be an output
pin regardless of the setting of the DDD1 bit in DDRD.

Data Reception

Figure 42 shows a block diagram of the UART Receiver.
Figure 42. UART Receiver
The receiver front-end logic samples the signal on the RXD pin at a frequency 16 times the baud rate. While the line is idle,
one single sample of logical "0" will be interpreted as the falling edge of a start bit and the start bit detection sequence is
initiated. Let sample 1 denote the first zero-sample. Following the 1-to-0 transition, the receiver samples the RXD pin at
samples 8, 9 and 10. If two or more of these three samples are found to be logical "1"s, the start bit is rejected as a noise
spike and the receiver starts looking for the next 1-to-0 transition.
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