Data Reception - Atmel ATmega161 Manual

Data Reception

ATmega161(L)
70
Figure 46 shows a block diagram of the UART receiver.
Figure 46. UART Receiver
BAUD RATE
XTAL
GENERATOR
PIN CONTROL
LOGIC
PD0/ RXDn
PB2
n = 0,1
The receiver front-end logic samples the signal on the RXDn pin at a frequency 16 times
the baud rate. While the line is idle, one single sample of logical "0" will be interpreted as
the falling edge of a start bit, and the start bit detection sequence is initiated. Let sample
1 denote the first zero-sample. Following the 1-to-0 transition, the receiver samples the
RXDn pin at samples 8, 9 and 10. If two or more of these three samples are found to be
logical "1"s, the start bit is rejected as a noise spike and the receiver starts looking for
the next 1-to-0 transition.
If, however, a valid start bit is detected, sampling of the data bits following the start bit is
performed. These bits are also sampled at samples 8, 9 and 10. The logical value found
in at least two of the three samples is taken as the bit value. All bits are shifted into the
transmitter shift register as they are sampled. Sampling of an incoming character is
shown in Figure 47. Note that the description above is not valid when the UART trans-
mission speed is doubled. See "Double-speed Transmission" on page 77 for a detailed
description.
DATA BUS
BAUD x 16
BAUD
/16
STORE UDRn
DATA RECOVERY
LOGIC
UART CONTROL AND
STATUS REGISTER
(UCSRnB)
DATA BUS
UART I/O DATA
REGISTER (UDRn)
10(11)-BIT RX
SHIFT REGISTER
UART CONTROL AND
STATUS REGISTER
(UCSRnA)
RXCn
IRQ
1228B–09/01