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Hot Swap Circuitry
The MCP750HA may be safely inserted and extracted from the system
chassis while power is applied. The hot swap circuitry will protect the
board from electrical damage. The MCP750HA uses an LTC1643 hot
swap controller device from Linear Technologies to implement hot swap
capability.
In systems that support high availability, the CPCI bus may be active while
the MCP750HA is inserted and/or removed without disturbing the bus
traffic. This is accomplished by pin-staged CPCI bus connections, a
switched pre-charged voltage level applied to bussed pins and three-stated
PCI-to-PCI bridge signals during insertion and removal.
The BD_SEL# signal from CPCI bus J1 pin D1 must be driven true (low)
for the back end power supplies to switch on. When BD_SEL# is not
asserted only a small portion of the MCP750HA circuitry is powered.
The HLTY# signal is driven true (low) to the CPCI bus J1 pin B4 when the
+5.0VDC, +3.3VDC, +12VDC, and -12VDC input power supplies are all
within tolerance. This can be used as a status indicator.
CompactPCI Interface
The CompactPCI bus interface will support up to 7 CompactPCI
peripheral cards. The CompactPCI bus interface is provided using the
DEC 21154 PCI-to-PCI bridge chip. This device implements a 64-bit
primary data bus and 64-bit secondary data bus interface and is PCI 2.1
compliant. The 21154 provides read/write data buffering in both
directions.
The MCP750HA uses an external arbiter which implements a level
rotating algorithm for all CompactPCI masters. The arbiter latency is
typically one PCI clock. If the arbiter detects that an initiator has failed to
assert FRAME# within 16 clock of the grant, the arbiter will negate the
grant. The arbiter parks the CPCI bus at the last bus master by keeping the
last grant asserted until a new bus request is asserted. After a reset, the
arbitter parks the CPCI bus at DEC21154 until a new request is asserted.
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Block Diagram
3
3-5
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